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An interface device to support a distributed parallel system for the StrongARM microprocessor

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High-Performance Computing and Networking (HPCN-Europe 1998)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1401))

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Abstract

This work describes a single chip interface between the StrongARM processor and the ICR C416 hardware message routing device. This allows the construction of a scaleable distributed parallel system with features similar to that of a transputer system but with the benefits of the higher clock speed and cache memory of the StrongARM. This interface has been implemented on an ALTFRA 10K FLEX series FPGA. The interface design and simulation results are outlined.

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References

  1. CRAY T3D, Cray Research Inc., Chippewa Falls, WI, USA.

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  2. B C O'Neill, et al, ‘Design and Exploitation of a 26,000 Gate Message Routing Device', Fifth EURCHIP Workshop on VLSI Design Training,, Germany, Oct. 1994, pp290–303.

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  3. Digital Semiconductors SA-110 Microprocessor Technical Reference Manual, EC-QPWLC-TE, DEC Ltd, Maynard, Massachusetts, USA, 1996.

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Peter Sloot Marian Bubak Bob Hertzberger

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© 1998 Springer-Verlag Berlin Heidelberg

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O'Neill, B.C. et al. (1998). An interface device to support a distributed parallel system for the StrongARM microprocessor. In: Sloot, P., Bubak, M., Hertzberger, B. (eds) High-Performance Computing and Networking. HPCN-Europe 1998. Lecture Notes in Computer Science, vol 1401. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0037266

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  • DOI: https://doi.org/10.1007/BFb0037266

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-64443-9

  • Online ISBN: 978-3-540-69783-1

  • eBook Packages: Springer Book Archive

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