Abstract
This work describes a single chip interface between the StrongARM processor and the ICR C416 hardware message routing device. This allows the construction of a scaleable distributed parallel system with features similar to that of a transputer system but with the benefits of the higher clock speed and cache memory of the StrongARM. This interface has been implemented on an ALTFRA 10K FLEX series FPGA. The interface design and simulation results are outlined.
References
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© 1998 Springer-Verlag Berlin Heidelberg
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O'Neill, B.C. et al. (1998). An interface device to support a distributed parallel system for the StrongARM microprocessor. In: Sloot, P., Bubak, M., Hertzberger, B. (eds) High-Performance Computing and Networking. HPCN-Europe 1998. Lecture Notes in Computer Science, vol 1401. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0037266
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DOI: https://doi.org/10.1007/BFb0037266
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