Abstract
An optimal systolic adder is mapped onto three different optoelectronic 3-D systems. It is shown that compared to the 2-D system the latency can be improved from o(√n) to o(n) and the period time from o(√n) to o(1).
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© 1996 Springer-Verlag Berlin Heidelberg
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Fey, D. (1996). Transformation of a 2-D VLSI systolic adder circuit in 3-D circuits using optical interconnections. In: Bougé, L., Fraigniaud, P., Mignotte, A., Robert, Y. (eds) Euro-Par'96 Parallel Processing. Euro-Par 1996. Lecture Notes in Computer Science, vol 1124. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0024739
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DOI: https://doi.org/10.1007/BFb0024739
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