Abstract
The presence of procedures and procedure calls introduces side effects, which complicate the analysis of stale reference detection in compiler-directed cache coherence schemes [4, 3, 10]. Previous compiler algorithms use the invalidation of an entire cache at procedure boundary [5, 8] or inlining [8] to avoid reference marking interprocedurally. However, frequent cache invalidations will result in poor performance since locality can not be exploited across the procedure boundary. Also, the inlining is often prohibitive due to both its code expansion and increase in its compilation time and memory requirements. In this paper, we introduce an improved intraprocedural and interprocedural algorithms for detecting references to stale data. The intraprocedural algorithm can mark potential stale references without relying on any cache invalidation or inlining at procedure boundaries, thus avoiding unnecessary cache misses for subroutine local data. The interprocedural algorithm performs bottom-up and top-down analysis on the procedure call graph to further exploit locality across procedure boundaries.
This work is supported in part by the National Science Foundation under Grant No. MIP 89-20891, MIP 93-07910.
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R. Ballance, A. Maccabe, and K. Ottenstein. The Program Dependence Web: a Representation Supporting Control-Data-and Demand-Driven Interpretation of Imperative Languages. Proceedings of the SIGPLAN '90 Conference on Programming Language Design and Implementation, pages 257–271, June 1990.
D. Callahan and K. Kennedy. Analysis of Interprocedural Side Effects in a Parallel Programming Environment. Journal of Parallel and Distributed Computing, 5:517–550, 1988.
Hoichi Cheong. Life Span Strategy — A Compiler-Based Approach to Cache Coherence. Proceedings of the 1992 International Conference on Supercomputing, July 1992.
Hoichi Cheong and Alex Veidenbaum. A Cache Coherence Scheme with Fast Selective Invalidation. Proceedings of The 15th Annual International Symposium on Computer Architecture, page 299, June 1988.
Hoichi Cheong and Alexander V. Veidenbaum. Stale Data Detection and Coherence Enforcement Using Flow Analysis. Proceedings of the 1988 International Conference on Parallel Processing, I, Architecture:138–145, August 1988.
Hoichi Cheong and Alexander V. Veidenbaum. A Version Control Approach To Cache Coherence. Proceedings of 1989 ACM/SIGARCH International Conference on Supercomputing, June 1989.
T. Chiueh. A Generational Approach to Software-Controlled Multiprocessor Cache Coherence. Proceedings 1993 International Conference on Parallel Processing, 1993.
Lynn Choi and Pen-Chung Yew. Eliminating Stale Data References through Array Data-Flow Analysis. CSRD Technical Report No. 1425, April. 1995.
Lynn Choi and Pen-Chung Yew. Interprocedural Array Data-Flow Analysis for Cache Coherence. CSRD Technical Report No. 1427, May. 1995.
Lynn Choi and Pen-Chung Yew. A Compiler-Directed Cache Coherence Scheme with Improved Intertask Locality. Proceedings of the Supercomputing'94, November 1994.
Mary W. Hall. Managing Interprocedural Optimization. Technical report, Rice University, Dept. of Computer Science, April 1991. Ph.D. Thesis.
Paul Havlak. Interprocedural Symbolic Analysis. Technical report, Rice University, Dept. of Computer Science, May 1994. Ph.D. Thesis.
A. Louri and H. Sung. A Compiler Directed Cache Coherence Scheme with Fast and Parallel Explicit Invalidation. Proceedings of the 1992 International Conference on Parallel Processing, I, Architecture:I-2–I-9, August 1992.
S. L. Min and J.-L. Baer. A Timestamp-based Cache Coherence Scheme. 1989 International Conference on Parallel Processing, I:23–32, 1989.
D. A. Padua, R. Eigenmann, J. Hoeflinger, P. Peterson, P. Tu, S. Weatherford, and K. Faign. Polaris: A New-Generation Parallelizing Compiler for MPPs. In CSRD Rept. No. 1306. Univ. of Illinois at Urbana-Champaign., June, 1993.
P. Tu and D. Padua. Gated SSA Based Demand-Driven Symbolic Analysis. CSRD Technical Report No. 1336, Feb. 1994.
A. V. Veidenbaum. A Compiler-Assisted Cache Coherence Solution for Multiprocessors. Proceedings of the 1986 International Conference on Parallel Processing, pages 1029–1035, August 1986.
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© 1996 Springer-Verlag Berlin Heidelberg
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Choi, L., Yew, P.C. (1996). Interprocedural array data-flow analysis for cache coherence. In: Huang, CH., Sadayappan, P., Banerjee, U., Gelernter, D., Nicolau, A., Padua, D. (eds) Languages and Compilers for Parallel Computing. LCPC 1995. Lecture Notes in Computer Science, vol 1033. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0014193
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DOI: https://doi.org/10.1007/BFb0014193
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