Abstract
Design extraction and reduction have been extensively used in modern VLSI design process. The extracted and reduced design can be efficiently processed by various applications, such as formal verification, simulation, automatic test pattern generation (ATPG). etc. This paper presents a new circuit extraction method using program slicing technique, and develops an elegant theoretical basis based on program slicing for circuit extraction from Verilog description. The technique can obtain achaining slice for given signals of interest. Compared with related researches, the main advantages of the method include that it is fine grain; it has no hardware description language (HDL) coding style limitation; it is precise and is capable of dealing with various Verilog constructions. The technique has been integrated with a commercial simulation environment and incorporated into a design process. The results of practical designs show the significant benefits of the approach.
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This work is supported by the National Natural Science Foundation of China (Grant No.60303011).
Tun Li received the B.E degree in 1996 and M.S. degree in 1999 both from National University of Defense Technology (NUDT). He is working toward the Ph.D. degree at NUDT. His areas of research include parallel logic simulation, microprocessor design verification.
Yang Guo received the B.E. degree in 1993, M.S. degree in 1996 and Ph.D. degree in 1999 from NUDT. He is now an assistant professor of Department of Computer Science and Technology of NUDT. His area of research includes microprocessor design verification.
Si-Kun Li is a professor of Department of Computer Science and Technology of NUDT. His areas of research include microprocessor design verification, virtual reality, VLSI design methodology, etc.
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Li, T., Guo, Y. & Li, SK. Automatic circuit extractor for HDL description using program slicing. J. Comput. Sci. & Technol. 19, 718–728 (2004). https://doi.org/10.1007/BF02945599
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DOI: https://doi.org/10.1007/BF02945599