Abstract
A novel method, named critical-network-based (CNB) for timing optimization in global routing is presented in this paper. The essence of this method is different from that of the typical existing ones, named nets-based (NB) and critical-path-based (CPB). The main contribution of this paper is that the CNB delay reduction method is more efficient than the typical existing ones. This new method makes it possible to reduce the delay in an overall survey. Based on CNB, a timing optimization algorithm for global routing is implemented and tested on Microelectronics Center of North Carolina (MCNC) benchmarks in this paper. The experimental results are compared between this algorithm and the existing ones. The experimental results show that this algorithm is able to control the delay efficiently.
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Jing T, Hong X L, Cai Y Cet al. The key technologies and related research work of performance-driven global routing.J. Software, 2001, 12(5): 677–688.
Jing T, Hong X L, Cai Y Cet al. Challenges to data-path physical design inside SOC.Chinese Journal of Semiconductors, 2002, 23(8): 785–793.
Elmore W C. The transient response of lumped linear networks with particular regard to wideband amplifiers.Journal of Applied Physics, 1948, 19(1): 55–59.
Chen C P, Chen Y P, Wong D F. Optimal wiresizing formula under the Elmore delay model. InProc. ACM/IEEE DAC, Las Vegas, Nevada, 1996, Session 26.4.
Sacurai T. Approximation of wiring delay in MOSFET LSI.IEEE Journal of Solid-State Circuits, 1983, 18(4): 418–426.
Yin L, He L. An efficient analytical model of coupled on-chip RLC interconnections. InProc. IEEE/ACM ASP-DAC, Yokohama, Japan, 2001, pp. 385–390.
Hong X L, Xue T X, Cheng C Ket al. Performance-driven Steiner tree algorithm for global routing. InProc. ACM/IEEE DAC, Dallas, Texas, 1993, pp. 177–181.
Bao H Y, Hong X L, Cai Y C. Timing-driven Steiner tree algorithm based on Sakurai model.Chinese J. Semiconductors, 1999, 20(1): 41–46.
Xu J Y, Hong X L, Jing Tet al. An efficient hier-archical timing-driven Steiner tree algorithm for global routing. InProc. IEE/ACM ASP-DAC, Bangalore, India, 2002, pp. 473–478.
Cong J, Leung K S. Optimal wiresizing under Elmore delay model.IEEE Trans. CAD, 1995, 14(3): 321–336.
Cong J, He L. Optimal wiresizing for interconnects with multiple sources.ACM Trans. Design Automation of Electronic Systems, 1996, 1(4): 478–511.
Cong J, He L, Cheng K Ket al. Interconnect design for deep submicron ICs. InProc. IEEE/ACM ICCAD, Los Alamitos, 1997.
Chris C N Chu, D F Wong. An efficient and optimal algorithm for simultaneous buffer and wire sizing.IEEE Trans. CAD, 1999, 18(9): 1297–1304.
Lillis J, Cheng C K. Timing optimization for multisource nets: characterization and optimal repeater insertion.IEEE Trans. CAD, 1999, 18(3): 322–331.
Alpert C J, Hrkic M, Hu Jet al. Buffered Steiner tree for difficult instances. InProc. ACM ISPD, 2001, pp. 4–9.
Swartz W, Sechen C. Timing driven placement for large standard cell circuits. InProc. ACM/IEEE DAC, 1995, pp. 211–215.
Jackson M, Kuh E S. Performance-driven placement of cell based IC’s. InProc. ACM/IEEE DAC, 1989, pp. 370–375.
Hu J, Sapatnekar S S. A timing-constrained algorithm for simultaneous global routing of multiple nets. InProc. IEEE/ACM ICCAD, 2000, pp. 99–103.
Huang J, Hong X L, Cheng C Ket al. An efficient timing-driven global routing algorithm. InProc. ACM/IEEE DAC, Dallas, TX, U.S.A., 1993, pp. 596–600.
Fujihara Y, Sekiyama Yet al. DYNAJUST: An efficient automation routing technique optimizing delay conditions. InProc. ACM/IEEE DAC, 1989, pp. 791–794.
Jackson M A B, Kuh E S, Marek-Sadowska M. Timing driven routing for building block layout. InProc. IEEE ISCAS, 1987, pp. 518–519.
Dunlop A E, Agrawal V Det al. Chip layout optimization using critical path weighting. InProc. ACM/IEEE DAC, 1984, pp. 133–136.
Rose M, Wiesel M, Kirkpatrick D, Nettleton N. Dense, performance directed, auto place and route. InProc. CICC, 1988, pp. 11.1.1–11.1.4.
Hong X L, Xue T X, Huang Jet al. TIGER: An efficient timing-driven global routing algorithm for standard cell and gate array design.IEEE Trans. CAD, 1997, 16(11): 1323–1331.
Bao H Y, Jing T, Hong X Let al. A novel random global routing algorithm independent of net ordering.Chinese J. Computers, 2001, 24(6): 574–579.
Jing T, Hong X L, Bao H Yet al. SSTT: Efficient local search for GSI global routing.J. Computer Science and Technology, 2003, 18(5): 632–639.
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This work was supported by the National Hi-Tech Development 863. Program of China under Grant No.2002AA1Z1 160, the National Grand Fundamental Research 973 Program of China under Grant No. G1998030403, the Specialized Research Fund for the Doctoral Program of Higher Education under Grant No.2002003008, the National Natural Science Foundation of China under Grant No.60121120706, the National Natural Science Foundation of USA under Grant No. CCR-0096383, and the Key Faculty Support Program of Tsinghua University under Grant No.[2002]4.
HONG XianLong was born in 1940. He is currently a chief professor at Department of Computer Science and Technollogy in Tsinghua University. P.R. China. His research interests include layout algorithms and systems.
For the biography ofJING Tong, please refer to P.639, No.5, Vol.18 of this journal.
For the biography ofXU JingYu please refer to P.639, No.5, Vol.18 of this journal.
For the biography ofBAO HaiYun, please refer to P.639, No.5, Vol.18 of this journal.
For the biography ofGU Jun, please refer to P.639, No.5, Vol.18 of this journal.
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Hong, X., Jing, T., Xu, J. et al. CNB: A critical-network-based timing optimization method for standard cell global routing. J. Comput. Sci. & Technol. 18, 732–738 (2003). https://doi.org/10.1007/BF02945461
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DOI: https://doi.org/10.1007/BF02945461