Abstract
Voltage controlled delay element (VCDE) is a basic building block in clocking circuits, especially in delay-locked loops (DLL). The VCDE is intended to generate an accurate and precise delay from a reference clock and it is expected to have linear delay characteristics with respect to the control voltage over a wide range. In addition, the VCDE needs to be robust across the process and temperature corners with low power consumption. The conventional delay elements such as current-starved inverter (CSI), wide-range CSI, triply controlled delay cell and digital controlled delay element lack one or more of the above mentioned features. In this paper, a robust, low-power, widely linear (over rail-to-rail control voltage range), charge-controlled, differential delay element circuit topology is proposed. The proposed circuit topology consists of a differential transmission gates along with a variable capacitors and it is implemented in 1.2 V, 65 nm CMOS technology. The performance results shows that it has a delay range of 80 ps to 120 ps over a control voltage range from rail-to-rail. The designed circuit topology is robust over PVT corners and exhibits a bandwidth of 500 MHz (1 GHz to 1.5 GHz) with a power consumption of 0.6 \(\upmu \)W and occupies an area of 0.0018 mm\(^2\).
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Kammari, R., Pasupureddi, V.S.R. (2019). A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_18
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DOI: https://doi.org/10.1007/978-981-32-9767-8_18
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