Nothing Special   »   [go: up one dir, main page]

Skip to main content

Technical Difficulties and Development Trend

  • Chapter
  • First Online:
Software Defined Chips

Abstract

Chapter 2 of Volumn I introduces the key issues to be considered in the research of SDC, while Chapters 3 and 4 of Volume I and Chapters 1 and 2 of Volume II introduce the design space of these key issues from different layers and perspectives.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 139.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 179.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 179.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Bird S, Phansalkar A, John L K, et al. Performance characterization of spec CPU benchmarks on intel’s core microarchitecture based processor[C]//SPEC Benchmark Workshop, 2007: 1–7

    Google Scholar 

  2. Liu L, Zhu J, Li Z et al (2019) A survey of coarse-grained reconfigurable architecture and design: Taxonomy, challenges, and applications[J]. ACM Comput Surv 52(6):1–39

    Article  Google Scholar 

  3. Sankaralingam K, Nagarajan R, Liu H et al (2004) TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP[J]. ACM Trans Arch Code Optim 1(1):62–93

    Article  Google Scholar 

  4. Park H, Park Y, Mahlke S (2009) Polymorphic pipeline array: A flexible multicore accelerator with virtualized execution for mobile multimedia applications[C]. In: Proceedings of the 42nd Annual IEEE/ACM international symposium on microarchitecture, 370–380

    Google Scholar 

  5. Prabhakar R, Zhang Y, Koeplinger D, et al. (2017) Plasticine: A reconfigurable architecture for parallel patterns[C]. In: The 44th annual international symposium on computer architecture, 389–402

    Google Scholar 

  6. Packirisamy V, Zhai A, Hsu W, et al. (2009) Exploring speculative parallelism in SPEC[C]. In: IEEE international symposium on performance analysis of systems and software, 77–88

    Google Scholar 

  7. Robatmili B, Li D, Esmaeilzadeh H, et al. How to implement effective prediction and forwarding for fusable dynamic multicore architectures[C]. In: The 19th International Symposium on High Performance Computer Architecture, 2013: 460–471

    Google Scholar 

  8. Chattopadhyay A. (2013) Ingredients of adaptability: A survey of reconfigurable processors[J]. VLSI Design

    Google Scholar 

  9. Karuri K, Chattopadhyay A, Chen X, et al. (2008) A design flow for architecture exploration and implementation of partially reconfigurable processors[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(10): 1281–1294

    Google Scholar 

  10. Stripf T, Koenig R, Becker JA (2011) Novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors[C]. In: International conference on embedded computer systems: architectures, modeling and simulation, 157–164

    Google Scholar 

  11. Bouwens F, Berekovic M, Kanstein A, et al. (2007) Architectural exploration of the ADRES coarse-grained reconfigurable array[C]. In: International workshop on applied reconfigurable computing, 1–13

    Google Scholar 

  12. Chin S A, Sakamoto N, Rui A, et al. (2017) CGRA-ME: A unified framework for CGRA modelling and exploration[C]. In: The 28th international conference on application-specific systems, architectures and processors (ASAP), 184–189

    Google Scholar 

  13. Suh D, Kwon K, Kim S, et al. (2012) Design space exploration and implementation of a high performance and low area coarse grained reconfigurable processor[C]. In: International conference on field-programmable technology, 67–70

    Google Scholar 

  14. Kim Y, Mahapatra R N, Choi K. (2009) Design space exploration for efficient resource utilization in coarse-grained reconfigurable architecture[J]. IEEE transactions on very large scale integration (VLSI) systems, 18(10): 1471–1482

    Google Scholar 

  15. George N, Lee H, Novo D, et al. (2014) Hardware system synthesis from domain-specific languages[C]. In: The 24th international conference on field programmable logic and applications (FPL), 1–8

    Google Scholar 

  16. Prabhakar R, Koeplinger D, Brown KJ et al (2016) Generating configurable hardware from parallel patterns[J]. ACM Sigplan Not 51(4):651–665

    Article  Google Scholar 

  17. Koeplinger D, Prabhakar R, Zhang Y, et al. (2016) Automatic generation of efficient accelerators for reconfigurable hardware[C]. In: The 43rd annual international symposium on computer architecture, 115–127

    Google Scholar 

  18. Li Z, Liu L, Deng Y, et al. (2017) Aggressive pipelining of irregular applications on reconfigurable hardware[C]. In: The 44th annual international symposium on computer architecture, 575–586

    Google Scholar 

  19. Nowatzki T, Gangadhar V, Ardalani N, et al. (2017) Stream-data flow acceleration[C]. In: The 44th annual international symposium on computer architecture,:416–429

    Google Scholar 

  20. Rau BR, Glaeser CD (1981) Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing[J]. ACM SIGMICRO Newsl 12(4):183–198

    Article  Google Scholar 

  21. Mei B, Vernalde S, Verkest D, et al. (2003) Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling[C]. In: Design, automation and test in europe conference and exhibition, 296–301

    Google Scholar 

  22. Hamzeh M, Shrivastava A, Vrudhula S. (2012) EPIMap: Using epimorphism to map applications on CGRAs[C]. In: Proceedings of the 49th annual design automation conference, 1284–1291

    Google Scholar 

  23. Hamzeh M, Shrivastava A, Vrudhula S (2013) REGIMap: Register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs)[C]. In: proceedings of the 50th annual design automation conference, 1–10

    Google Scholar 

  24. Swanson S, Schwerin A, Mercaldi M et al (2007) The wavescalar architecture[J]. ACM Trans Comput Syst 25(2):1–54

    Article  Google Scholar 

  25. Voitsechov D, Etsion Y (2014) Single-graph multiple flows: Energy efficient design alternative for GPGPUs[J]. ACM SIGARCH Comput Arch News 42(3):205–216

    Article  Google Scholar 

  26. Singh H, Lee M, Lu G et al (2000) MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications[J]. IEEE Trans Comput 49(5):465–481

    Article  Google Scholar 

  27. Mei B, Vernalde S, Verkest D, et al. (2003) ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix[C]. In: International conference on field programmable logic and applications, 61–70

    Google Scholar 

  28. Govindaraju V, Ho C, Nowatzki T et al (2012) Dyser: Unifying functionality and parallelism specialization for energy-efficient computing[J]. IEEE Micro 32(5):38–51

    Article  Google Scholar 

  29. Goldstein SC, Schmit H, Budiu M et al (2000) PipeRench: A reconfigurable architecture and compiler[J]. Computer 33(4):70–77

    Article  Google Scholar 

  30. Pager J, Jeyapaul R, Shrivastava A (2015) A software scheme for multithreading on CGRAs[J]. ACM Trans Embed Comput Syst 14(1):1–26

    Article  Google Scholar 

  31. Chang K, Choi K (2008) Mapping control intensive kernels onto coarse-grained reconfigurable array architecture[C]. In: International SoC Design Conference, 362

    Google Scholar 

  32. Lee G, Chang K, Choi K (2010) Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution[C]. In: ieee international symposium on parallel & distributed processing, workshops and PHD forum, 1–4

    Google Scholar 

  33. Parashar A, Pellauer M, Adler M et al (2014) Efficient spatial processing element control via triggered instructions[J]. IEEE Micro 34(3):120–137

    Article  Google Scholar 

  34. Mahlke SA, Hank RE, McCormick JE, et al. (1995) A comparison of full and partial predicated execution support for ILP processors[C]. In: Proceedings of the 22nd annual international symposium on computer architecture, 138–150

    Google Scholar 

  35. Kim C, Sethumadhavan S, Govindan M S, et al. (2007) Composable lightweight processors[C]. In:The 40th annual IEEE/ACM international symposium on microarchitecture, 381–394

    Google Scholar 

  36. Mahlke SA, Lin DC, Chen WY et al (1992) Effective compiler support for predicated execution using the hyperblock[J]. ACM SIGMICRO Newsl 23(1–2):45–54

    Article  Google Scholar 

  37. Kagi A, Goodman JR, Burger D (1996) Memory bandwidth limitations of future microprocessors[C]. In: The 23rd annual international symposium on computer architecture, 78.

    Google Scholar 

  38. Jafri S M, Hemani A, Paul K, et al. (2011) Compression based efficient and agile configuration mechanism for coarse grained reconfigurable architectures[C]. In: IEEE international symposium on parallel and distributed processing, workshops and PHD forum, 290–293

    Google Scholar 

  39. Kim Y, Mahapatra RN (2009) Dynamic context compression for low-power coarse-grained reconfigurable architecture[J]. IEEE transactions on very large scale integration (VLSI) systems, 18(1): 15–28

    Google Scholar 

  40. Suzuki M, Hasegawa Y, Tuan VM, et al. (2006) A cost-effective context memory structure for dynamically reconfigurable processors[C]. In: The 20th IEEE International Parallel & Distributed Processing Symposium, 8

    Google Scholar 

  41. Saporito A (2020) The IBM z15 processor chip set[C]. IEEE hot Chips 32 symposium, 1–17

    Google Scholar 

  42. Tu F, Wu W, Yin S, et al. (2018) RANA: Towards efficient neural acceleration with refresh-optimized embedded DRAM[C]. In: The 45th annual international symposium on computer architecture, 340–352

    Google Scholar 

  43. Norrie T, Patil N, Yoon D H, et al. (2020) Google’s training chips revealed: TPUv2 and TPUv3[C]//IEEE Hot Chips 32 Symposium (HCS), IEEE Comput Soc, 1–70

    Google Scholar 

  44. Gao M, Kozyrakis C. HRL: Efficient and flexible reconfigurable logic for near-data processing[C]. In: IEEE international symposium on high performance computer architecture, 2016: 126–137

    Google Scholar 

  45. Farmahini-Farahani A, Ahn JH, Morrow K, et al. (2015) NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules[C]. In: The 21st international symposium on high performance computer architecture, 283–295

    Google Scholar 

  46. Patterson D, Anderson T, Cardwell N et al (1997) A case for intelligent RAM[J]. IEEE Micro 17(2):34–44

    Article  Google Scholar 

  47. Seshadri V, Lee D, Mullins T, et al. (2017) Ambit: In-memory accelerator for bulk bitwise operations using commodity DRAM technology[C]. In:The 50th annual IEEE/ACM international symposium on microarchitecture, 273–287

    Google Scholar 

  48. Li S, Niu D, Malladi K T, et al. (2017) Drisa: A dram-based reconfigurable in-situ accelerator[C]. In: The 50th annual IEEE/ACM international symposium on microarchitecture, 288–301.

    Google Scholar 

  49. Zhang J, Wang Z, Verma N (2016) A machine-learning classifier implemented in a standard 6T SRAM array[C]. In: IEEE symposium on VLSI circuits (VLSI-Circuits), 1–2

    Google Scholar 

  50. Chen D, Li Z, Xiong T, et al. (2020) CATCAM: Constant-time alteration ternary CAM with scalable in-memory architecture[C]. In: The 53rd annual IEEE/ACM international symposium on microarchitecture, 342–355

    Google Scholar 

  51. Eckert C, Wang X, Wang J, et al. (2018) Neural cache: Bit-serial in-cache acceleration of deep neural networks[C]. In: The 45th annual international symposium on computer architecture, 383–396

    Google Scholar 

  52. Guo Q, Guo X, Patel R, et al. (2013) AC-DIMM: Associative computing with STT-MRAM[C] In: Proceedings of the 40th annual international symposium on computer architecture, 189–200

    Google Scholar 

  53. Chi P, Li S, Xu C et al (2016) Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory[J]. ACM SIGARCH Comput Arch News 44(3):27–39

    Article  Google Scholar 

  54. Sebastian A, Tuma T, Papandreou N et al (2017) Temporal correlation detection using computational phase-change memory[J]. Nat Commun 8(1):1–10

    Article  Google Scholar 

  55. Cong J, Huang H, Ma C, et al. (2014) A fully pipelined and dynamically composable architecture of CGRA[C]. In: The 22nd annual international symposium on Field-programmable custom computing machines, 9–16

    Google Scholar 

  56. Chen Y, Krishna T, Emer JS et al (2016) Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks[J]. IEEE J Solid-State Circuits 52(1):127–138

    Article  Google Scholar 

  57. Ciricescu S, Essick R, Lucas B, et al. (2003) The reconfigurable streaming vector processor (RSVP/spl trade/)[C]. In: The 36th annual IEEE/ACM international symposium on microarchitecture, 141–150.

    Google Scholar 

  58. Ho C, Kim SJ, Sankaralingam K (2015) Efficient execution of memory access phases using data flow specialization[C]. In: Proceedings of the 42nd annual international symposium on computer architecture, 118–130

    Google Scholar 

  59. Jain AK, Maskell DL, Fahmy SA. (2016) Are coarse-grained overlays ready for general purpose application acceleration on fpgas?[C]. In: The 14th international conference on dependable, autonomic and secure computing, the 14th international conference on pervasive intelligence and computing, the 2nd international conference on big data intelligence and computing and cyber science and technology congress, 586–593

    Google Scholar 

  60. Liu C, Ng H, So HK (2015) QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay[C]. In: International conference on field programmable technology, 56–63

    Google Scholar 

  61. Khawam S, Nousias I, Milward M, et al. (2007) The reconfigurable instruction cell array[J]. IEEE transactions on very large scale integration (VLSI) systems, 16(1): 75–85

    Google Scholar 

  62. Venkatesh G, Sampson J, Goulding N et al (2010) Conservation cores: Reducing the energy of mature computations[J]. ACM Sigplan Not 45(3):205–218

    Article  Google Scholar 

  63. Waingold E, Taylor M, Srikrishna D et al (1997) Baring it all to software: Raw machines[J]. Computer 30(9):86–93

    Article  Google Scholar 

  64. Swanson S, Michelson K, Schwerin A, et al. (2003) WaveScalar[C]. In: Proceedings of the 36th annual IEEE/ACM international symposium on microarchitecture, 291–302

    Google Scholar 

  65. Bondalapati K, Prasanna VK (2002) Reconfigurable computing systems[J]. Proc IEEE 90(7):1201–1217

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Leibo Liu .

Rights and permissions

Reprints and permissions

Copyright information

© 2023 Science Press

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Liu, L., Wei, S., Zhu, J., Deng, C. (2023). Technical Difficulties and Development Trend. In: Software Defined Chips. Springer, Singapore. https://doi.org/10.1007/978-981-19-7636-0_3

Download citation

  • DOI: https://doi.org/10.1007/978-981-19-7636-0_3

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-19-7635-3

  • Online ISBN: 978-981-19-7636-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics