Abstract
Hardware security is becoming a major concern and threat due to the emerging hardware Trojan attacks. The threat poses due to malicious hardware Trojans during SoC life cycles are major causes of a security breach, financial theft and malfunctioning of SoCs. An attacker may mount such an attack by keeping the goal of operation failure or information leakage. Today’s SoC design and fabrication processes involve untrusted parties at different stages of the IC life cycle. Therefore, it increases the vulnerability of such attacks. In this paper, we have inserted hardware Trojans to low-probability nodes of ISCAS combinational benchmark circuits to mimic the real-life scenario. We propose the novel transition probability-based technique to detect the insertion of malicious hardware Trojan. The technique is performed by calculating probabilities on each net before and after Trojan insertion. Experimental results show that a logical OR gate as a Trojan gate has a minimal effect on the transition probability of primary outputs compared to all other logic gates.
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Acknowledgments
The authors are thankful to Dr. K.S. Dasgupta and Dr. Virendra Singh for their guidance, reviews and constructive suggestions for this research work.
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Mehta, U., Popat, J. (2022). Transition Probability-Based Detection of Hardware Trojan in Digital Circuits. In: Yang, XS., Sherratt, S., Dey, N., Joshi, A. (eds) Proceedings of Sixth International Congress on Information and Communication Technology. Lecture Notes in Networks and Systems, vol 235. Springer, Singapore. https://doi.org/10.1007/978-981-16-2377-6_57
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DOI: https://doi.org/10.1007/978-981-16-2377-6_57
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