Abstract
Due to the memory size increase drastically in the field programable gate array (FPGA) or system on chip (SOC) device, it become hard to meet the tests cost budget of the product especially for low-cost device. One of the major factors of test cost contributed is the test time. For the low-cost product, the tolerance number of the defects per million (DPM) are relative high compare to high cost product. By taking this advantage, an optimizing memory testing method able to implement to minimize the test time without jeopardize the test coverage. A memory Build-in Self-test (BIST) design with capability of algorithm failing sequence capture have been developed to implement in the Automate Test Equipment (ATE) flow for production screen. 3 selected algorithms have been tested on the 8 detect units in ATE flow to prove the concept of this method. The failing algorithm sequence of the units have been logged into database and analyzed for algorithm trimming. With the proper examples, the algorithm trimming location and test time saving calculation have been shown in this research. For this example, approximate 33% of test time reduction observed for 1 Kbyte memory testing with Hammer Head algorithm. In summary, this research has proposed the memory test time saving by optimizing the tests algorithm on the ATE flow.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Kaushik, S., Zorian, Y.: Embedded memory test and repair optimizes SoC yield in. http://www.edn.com. 17th July 2012
Mohammed, B.: Embedded memory interface logic and interconnect testing. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23(9), 1946–1950 (2015)
Mishra, D.K., Solanki, R.: Implementation of BIST architecture for testing SRAM cell using dynamic supply current. In: IRF International Conference, Bengaluru, June 2014, pp. 27–32 (2014)
Joseph, P.E., Antony P.R.: VLSI design and comparative analysis of memory BIST controllers. In: First International Conference on Computational Systems and Communications, Trivandrum, 17–18 December 2014 (2014)
Ramana Kumari, K.L.V., Asha Rani, M., Balaji, N.: FPGA implementation of memory design and testing. In: IEEE 7th International Advance Computing Conference (IACC) (2017)
Andrienko, V.A., Diaa, M., Ryabtsev, V.G., Utkina, T.Yu.: Architecture of built-in self-test and recovery memory chips. In: IEEE (2013)
Linder, M., Eder, A., Oberlander, K., Schlichtmann, U.: An analysis of industrial SRAM test results. In: Design & Test, IEEE, 28 August 2013–22 July 2015, pp. 42–51 (2015)
Singh, B., Khosla, A., Narang, S.B.: Area overhead and power analysis of March algorithms for memory BIST. In: International Conference on Communication Technology and System Design 2012, vol. 30, pp. 930–936 (2012)
Mohammad, B., Eleyan, N., Seok, G., Kim, H.: Automated flow for generation CMOS custom memory bit map. In: Proceedings IEEE International Design Test Symposium (IDTS), December 2013, pp. 1–6 (2013)
Acknowledgements
The authors would like to thank the referees and editors for providing very helpful comments and suggestions. This project was supported by Research University Grant, Universiti Sains Malaysia (1001/PELECT/8014160).
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2022 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Wahab, A.A.A., Alhady, S.S.N., Othman, W.A.F.W., Husin, H., Adnan, N.Q.M. (2022). Optimizing RAM Testing Method for Test Time Saving Using Automatic Test Equipment. In: Mahyuddin, N.M., Mat Noor, N.R., Mat Sakim, H.A. (eds) Proceedings of the 11th International Conference on Robotics, Vision, Signal Processing and Power Applications. Lecture Notes in Electrical Engineering, vol 829. Springer, Singapore. https://doi.org/10.1007/978-981-16-8129-5_41
Download citation
DOI: https://doi.org/10.1007/978-981-16-8129-5_41
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-16-8128-8
Online ISBN: 978-981-16-8129-5
eBook Packages: Intelligent Technologies and RoboticsIntelligent Technologies and Robotics (R0)