Nothing Special   »   [go: up one dir, main page]

Skip to main content

A Binary Translation Backend Registers Allocation Algorithm Based on Priority

  • Conference paper
  • First Online:
Geo-Spatial Knowledge and Intelligence (GSKI 2017)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 849))

Included in the following conference series:

Abstract

As most binary translation systems don’t consider the difference of register requirements of basic blocks, which brings redundant memory access instructions caused by unnecessary registers overflow. To solve this problem, a binary translation backend registers allocation algorithm based on priority (BTBRAP) is proposed. Firstly, local global register is allocated statically to reduce the global register maintenance overhead, according to the statistical features of registers on the source platform. Then, the number of every register requested in basic blocks is determined, according to the relationship between intermediate representation and the source platform registers. So the priority of registers allocation is obtained. Conclusively, allocate the registers dynamically based on the priority to reduce the registers overflow. As the test results of nbench, representative recursive programs and SPEC2006 show, the algorithm effectively reduces the redundant memory access of local code, and improves the program performance with an average increase of 7.94%.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Similar content being viewed by others

References

  1. Altman, E.R., Kaeli, D., Sheffer, Y.: Welcome to the opportunities of binary translation. J. Comput. 33(3), 40–45 (2000)

    Google Scholar 

  2. Ma, J., Li, Z., Hu, C., et al.: A reconstruction method of type abstraction in binary code. J. Comput. Res. Dev. 50(11), 2418–2428 (2013)

    Google Scholar 

  3. Chen, J.S., Lan, X.H., Wei, Z.: Software transplant based on instruction simulation. J. Electron. Instrum. Customer (2010)

    Google Scholar 

  4. Muth, R.: Register liveness analysis of executable code. Manuscript, Department of Computer Science, the University of Arizona, December 1998

    Google Scholar 

  5. Ma, X., Wu, C., Tang, F., et al.: Two condition code optimization approaches in binary translation. J. Comput. Res. Dev. 42(2), 329–337 (2005)

    Article  Google Scholar 

  6. Liang, A., Guan, H., Li, Z.: A research on register mapping strategies of QEMU. In: 2nd International Symposium on Intelligence Computation and Application (2007)

    Google Scholar 

  7. Wen, Y., Tang, D., Ql, F.: Register mapping and register function cutting out implementation in binary translation. J. Softw. 20(2), 1–7 (2009)

    Google Scholar 

  8. Liao, Y., Sun Z.G., Jiang, H., et al.: All registers direct mapping method in dynamic binary translation. J. Comput. Appl. Softw. 28(11), 21–24 (2011)

    Google Scholar 

  9. Cai, Z., Liang, A., Qi, Z., et al.: Performance comparison of register allocation algorithms in dynamic binary translation. In: International Conference on Knowledge and Systems Engineering, pp. 113–119. IEEE (2009)

    Google Scholar 

  10. Liang, Y., Shao, Y., Yang, G., et al.: Register allocation for QEMU dynamic binary translation systems. Int. J. Hybrid Inf. Technol. 8(2), 199–210 (2015)

    Google Scholar 

  11. Bellard, F.C.: QEMU, a fast and portable dynamic translator. In: Conference on Usenix Technical Conference, p. 41. USE-NIX Association (2005)

    Google Scholar 

  12. Jiang, J., Wang, C., Wei, H.: An optimization strategy for local register allocation. J. Comput. Appl. Softw. 12, 215–217 (2013)

    Google Scholar 

  13. Zhang, X., Guo, X., Zhao, L.: Study on TCG dynamic binary translation technique. J. Comput. Appl. Softw. 30(11), 34–37 (2013)

    Google Scholar 

  14. Dai, T., Shan, Z., Lu, S., et al.: Register allocation algorithm of dynamic binary translation based on priority. J. Zhejiang Univ. (Eng. Sci.) 50(1), 158–165 (2016)

    Google Scholar 

  15. Smith, T.F., Waterman, M.S.: Identification of common molecular subsequences. J. Mol. Biol. 147, 195–197 (1981)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding authors

Correspondence to Jun Wang or Jianmin Pang .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer Nature Singapore Pte Ltd.

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Wang, J., Pang, J., Fu, L., Shan, Z., Yue, F., Zhang, J. (2018). A Binary Translation Backend Registers Allocation Algorithm Based on Priority. In: Yuan, H., Geng, J., Liu, C., Bian, F., Surapunt, T. (eds) Geo-Spatial Knowledge and Intelligence. GSKI 2017. Communications in Computer and Information Science, vol 849. Springer, Singapore. https://doi.org/10.1007/978-981-13-0896-3_41

Download citation

  • DOI: https://doi.org/10.1007/978-981-13-0896-3_41

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-13-0895-6

  • Online ISBN: 978-981-13-0896-3

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics