Abstract
JPEG (Joint Photographic Experts Group) XS is a new international standard targeting mezzanine compression with features of low complexity and low latency. It is designed extremely parallelizable and simple to implement on modern CPU, GPU, FPGA and ASIC. This paper proposes an efficient hardware JPEG XS encoder implementation. In this design, JPEG XS encoder is clearly decoupled into sub-modules that are pipelined and parallelized to effectively increase system throughput. The carefully crafted Rate Control module takes up a few cycles while reducing the use of hardware resources. The well-designed hardware architecture is suitable to be implemented using Xilinx HLS Tool and operates at 196 MHz on Alveo U50, achieving encoding speed of 8K 42 fps. The restored images usually yield a PSNR over 50 dB when bitrate is larger than 8.0 bpp.
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Yang, D., Chen, L. (2023). FPGA-Based Hardware Implementation of JPEG XS Encoder. In: Zhai, G., Zhou, J., Yang, H., Yang, X., An, P., Wang, J. (eds) Digital Multimedia Communications. IFTC 2022. Communications in Computer and Information Science, vol 1766. Springer, Singapore. https://doi.org/10.1007/978-981-99-0856-1_14
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DOI: https://doi.org/10.1007/978-981-99-0856-1_14
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