Abstract
In this chapter we define what a mixed-time-criticality system is and what its requirements are. After defining the concepts that such systems should follow, we described CompSOC, which is one example of a mixed-time-criticality platform. We describe, in detail, how multiple resources, such as processors, memories, and interconnect, are combined into a larger hardware platform, and especially how they are shared between applications using different arbitration schemes. Following this, the software architecture that transforms the single hardware platform into multiple virtual execution platforms, one per application, is described.
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Abbreviations
- AHB:
-
Advanced High-performance Bus
- ASIC:
-
Application-Specific Integrated Circuit
- AXI:
-
Advanced eXtensible Interface
- BD:
-
Budget Descriptor
- CCSP:
-
Credit-Controlled Static Priority
- CDC:
-
Clock Domain Crossing
- CM:
-
Communication Memory
- DLMB:
-
Data Local Memory Bus
- DMA:
-
Direct Memory Access
- DMAMEM:
-
DMA Memory
- DMEM:
-
Data Memory
- DRAM:
-
Dynamic Random-Access Memory
- ELF:
-
Executable and Linkable Format
- ET:
-
Execution Time
- ETSCH:
-
Extended TSCH
- FBSP:
-
Frame-Based Static Priority
- FIFO:
-
First-In First-Out
- FPGA:
-
Field-Programmable Gate Array
- GALS:
-
Globally Asynchronous Locally Synchronous
- ILMB:
-
Instruction Local Memory Bus
- IMEM:
-
Instruction Memory
- I/O:
-
Input/Output
- IP:
-
Intellectual Property
- IPB:
-
Intellectual Property Block
- KPN:
-
Kahn Process Network
- MAC:
-
Media Access Control
- MMIO:
-
Memory-Mapped I/O
- MPSoC:
-
Multi-Processor System-on-Chip
- NI:
-
Network Interface
- NoC:
-
Network-on-Chip
- PLB:
-
Processor Local Bus
- RR:
-
Round Robin
- RT:
-
Response Time
- RTOS:
-
Real-Time Operating System
- SI:
-
Scheduling Interval
- SoC:
-
System-on-Chip
- SPI:
-
Serial Peripheral Interface
- SRAM:
-
Static Random-Access Memory
- TDM:
-
Time-Division Multiplexing
- TFT:
-
Thin-Film Transistor
- TIFU:
-
Timer, Interrupt, and Frequency Unit
- TSCH:
-
Time-Synchronised Channel Hopping
- TTA:
-
Transport-Triggered Architecture
- UART:
-
Universal Asynchronous Receiver/Transmitter
- VEP:
-
Virtual Execution Platform
- WCET:
-
Worst-Case Execution Time
- WCRT:
-
Worst-Case Response Time
References
Akesson B, Goossens K (2011) Architectures and modeling of predictable memory controllers for improved system integration. In: Proceedings of design, automation and test in Europe conference and exhibition (DATE), Grenoble. IEEE, pp 1–6
Akesson B, Goossens K (2011) Memory controllers for real-time embedded systems. Embedded systems series, 1st edn. Springer, New York
Akesson B, Hansson A, Goossens K (2009) Composable resource sharing based on latency-rate servers. In: Proceedings of Euromicro symposium on digital system design (DSD), Patras, pp 547–555
Akesson B, Molnos A, Hansson A, Ambrose Angelo J, Goossens K (2010) Composability and predictability for independent application development, verification, and execution. In: Hübner M, Becker J (eds) Multiprocessor system-on-chip – hardware design and tool integration, circuits and systems, chap. 2 Springer, Heidelberg, pp 25–56
Akesson B, Steffens L, Strooisma E, Goossens K (2008) Real-time scheduling using credit-controlled static-priority arbitration. In: Proceedings of international conference on embedded and real-time computing systems and applications (RTCSA). IEEE Computer Society, Washington, DC, pp 3–14
Beyranvand Nejad A, Molnos A, Goossens K (2013) A software-based technique enabling composable hierarchical preemptive scheduling for time-triggered applications. In: Proceedings of international conference on embedded and real-time computing systems and applications (RTCSA), Taipei
Bini E, Buttazzo G, Eker J, Schorr S, Guerra R, Fohler G, Arzen KE, Romero Segovia V, Scordino C (2011) Resource management on multicore systems: the ACTORS approach. Proc Microarch (MICRO) 31(1):72–81
Bolder J, Oomen T (2014) Rational basis functions in iterative learning control – with experimental verification on a motion system. IEEE Trans Control Syst Technol 23(2):722–729
Chandrasekar K, Akesson B, Goossens K (2012) Run-time power-down strategies for real-time SDRAM memory controllers. In: Proceedings of design automation conference (DAC). ACM, New York, pp 988–993
Davis RI, Burns A (2011) A survey of hard real-time scheduling for multiprocessor systems. ACM Comput Surv (CSUR) 43(4):35
Edwards SA, Lee EA (2007) The case for the precision timed (pret) machine. In: Proceedings of the 44th annual design automation conference, New York. ACM, pp 264–265
Giannopoulou G, Stoimenov N, Huang P, Thiele L, de Dinechin BD (2015) Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources. J Real-Time Syst 52(4):399–449
Goossens S, Akesson B, Goossens K (2013) Conservative open-page policy for mixed time-criticality memory controllers. In: Proceedings of design, automation and test in Europe conference and exhibition (DATE), Grenoble, pp 525–530
Goossens K, Azevedo A, Chandrasekar K, Gomony MD, Goossens S, Koedam M, Li Y, Mirzoyan D, Molnos A, Beyranvand Nejad A, Nelson A, Sinha S (2013) Virtual execution platforms for mixed-time-criticality systems: the CompSOC architecture and design flow. ACM Spec Interest Group Embed Syst (SIGBED) Rev 10(3):23–34
Goossens K, Hansson A (2010) The Aethereal network on chip after ten years: goals, evolution, lessons, and future. In: Proceedings of design automation conference (DAC), Anaheim, pp 306–311
Goossens K, Koedam M, Sinha S, Nelson A, Geilen M (2015) Run-time middleware to support real-time system scenarios. In: Proceedings of European conference on circuit theory and design (ECCTD), Trondheim
Goossens S, Kouters T, Akesson B, Goossens K (2012) Memory-map selection for firm real-time SDRAM controllers. In: Proceedings of design, automation and test in Europe conference and exhibition (DATE). IEEE, Dresden, pp 828–831
Goossens S, Kuijsten J, Akesson B, Goossens K (2013) A reconfigurable real-time SDRAM controller for mixed time-criticality systems. In: International conference on hardware/software codesign and system synthesis (CODES+ISSS), Montreal, pp 1–10
Hansson A, Ekerhult M, Molnos A, Milutinovic A, Nelson A, Ambrose J, Goossens K (2011) Design and implementation of an operating system for composable processor sharing. J Micromech Microeng (MICPRO) 35(2):246–260. Elsevier. Special issue on network-on-chip architectures and design methodologies
Hansson A, Goossens K (2007) Trade-offs in the configuration of a network on chip for multiple use-cases. In: Proceedings of international symposium on networks on chip (NOCS). IEEE Computer Society, Washington, DC, pp 233–242
Hansson A, Goossens K (2009) An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. In: International conference on hardware/software codesign and system synthesis (CODES+ISSS). ACM, New York, pp 99–108
Hansson A, Goossens K (2010) On-Chip interconnect with aelite: composable and predictable systems. Embedded systems series. Springer, New York
Hansson A, Goossens K, Bekooij M, Huisken J (2009) CoMPSoC: a template for composable and predictable multi-processor system on chips. ACM Trans Des Autom Electron Syst 14(1):1–24
Hansson A, Wiggers M, Moonen A, Goossens K, Bekooij M (2009) Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis. IET Comput Digit Tech 3(5):398–412
Henzinger TA, Horowitz B, Kirsch CM (2003) Giotto: a time-triggered language for embedded programming. Proc IEEE 91(1):84–99
Jansen B, Schwiegelshohn F, Koedam M, Duhem F, Masing L, Werner S, Huriaux C, Courtay A, Wheatley E, Goossens K, Lemonnier F, Millet P, Becker J, Sentieys O, Hübner M (2015) Designing applications for heterogeneous many-core architectures with the FlexTiles platform. In: Proceedings of International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), Samos
Kasapaki E, Sorensen RB, Müller C, Goossens K, Schoeberl M, Sparso J (2015) Argo: a real-time network-on-chip architecture with an efficient GALS implementation. IEEE Trans Very Large Scale Integr Syst (TVLSI) 99(2):479–492
Kirsch C, Sokolova A (2012) The logical execution time paradigm. In: Chakraborty S, Eberspächer J (eds) Advances in real-time systems (ARTS). Springer, Berlin/Heidelberg, pp 103–120
Kopetz H (2011) Real-time systems: design principles for distributed embedded applications. Springer, Heidelberg
Li Y, Salunkhe H, Bastos J, Moreira O, Akesson B, Goossens K (2015) Mode-controlled data-flow modeling of real-time memory controllers. In: Proceedings of embedded systems for real-time multimedia (ESTIMedia), Amsterdam
Moreira O, Corporaal H (2014) Scheduling real-time streaming applications onto an embedded multiprocessor. Embedded systems series, vol 24. Springer, Cham
Nejad AB, Molnos A, Goossens K (2013) A unified execution model for multiple computation models of streaming applications on a composable MPSoC. J Syst Archit (JSA) 59(10, part C), 1032–1046. Elsevier
Nejad AB, Molnos A, Martinez ME, Goossens K (2013) A hardware/software platform for QoS bridging over multi-chip NoC-based systems. J Parallel Comput (PARCO)39(9):424–441. Elsevier
Nelson A (2014) Composable and predictable power management. Ph.D. thesis, Delft University of Technology
Nelson A, Beyranvand Nejad A, Molnos A, Koedam M, Goossens K (2014) CoMik: a predictable and cycle-accurately composable real-time microkernel. In: Proceedings of design, automation and test in Europe conference and exhibition (DATE), Dresden
Nelson A, Goossens K (2015) Distributed power management of real-time applications on a GALS multiprocessor SOC. In: Proceedings of ACM international conference on embedded software (EMSOFT), Amsterdam
Nelson A, Goossens K, Akesson B (2015) Dataflow formalisation of real-time streaming applications on a composable and predictable multi-processor SOC. J Syst Archit (JSA) 61(9):435–448
Nelson A, Molnos A, Goossens K (2011) Composable power management with energy and power budgets per application. In: Proceedings of international conference on embedded computer systems: architectures, modeling and simulation (SAMOS), Samos, pp 396–403
Nelson A, Molnos A, Goossens K (2012) Power versus quality trade-offs for adaptive real-time applications. In: Proceedings of embedded systems for real-time multimedia (ESTIMedia), Tampere, pp 75–84
Nesbit KJ, Smith JE, Moreto M, Cazorla FJ, Ramirez A, Valero M (2008) Multicore resource management. Proc Microarch (MICRO) 28(3):6–16
Nieuwland A, Kang J, Gangwal OP, Sethuraman R, Busá N, Goossens K, Peset Llopis R, Lippens P (2002) C-HEAP: a heterogeneous multi-processor architecture template and scalable and flexible protocol for the design of embedded signal processing systems. ACM Trans Des Autom Embed Syst 7(3):233–270
Obermaisser R, Weber D (2014) Architectures for mixed-criticality systems based on networked multi-core chips. In: Proceedings of Conference on Emerging Technology and Factory Automation (ETFA), Barcelona, pp 1–10
Pelz G et al (2005) Automotive system design and autosar. In: Advances in design and specification languages for SoCs. Springer, New York, pp 293–305
Pinho LM, Nelis V, Yomsi PM, Quinones E, Bertogna M, Burgio P, Marongiu A, Scordino C, Gai P, Ramponi M, Mardiak M (2015) P-socrates: a parallel software framework for time-critical many-core systems. J Microprocess Microsyst 39(8):1190–1203. Elsevier
Rădulescu A, Dielissen J, González Pestana S, Gangwal OP, Rijpkema E, Wielage P, Goossens K (2005) An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network programming. IEEE Trans CAD Integr Circuits Syst 24(1):4–17
Rushby J (1999) Partitioning in avionics architectures: requirements, mechanisms, and assurance. Technical report, NASA
Schoeberl M, Abbaspour S, Akesson B, Audsley N, Capasso R, Garside J, Goossens K, Goossens S, Hansen S, Heckmann R, Hepp S, Huber B, Jordan A, Kasapaki E, Knoop J, Li Y, Prokesch D, Puffitsch W, Puschner P, Rocha A, Silva C, Sparsø J, Tocchi A (2015) T-CREST: time-predictable multi-core architecture for embedded systems. J Syst Archit (JSA) 61(9):449–471. Elsevier
Sinha S, Koedam M, Breaban G, Nelson A, Nejad A, Geilen M, Goossens K (2015) Composable and predictable dynamic loading for time-critical partitioned systems on multiprocessor architectures. J Microprocess Microsyst (MICPRO) 39(8):1087–1107
Stefan R, Molnos A, Goossens K (2014) dAElite: a TDM NoC supporting QoS, multicast, and fast connection set-up. IEEE Trans Comput 63(3):583–594
Stuijk S, Basten T, Geilen M, Corporaal H (2007) Multiprocessor resource allocation for throughput-constrained synchronous dataflow graphs. In: Proceedings of design automation conference (DAC), San Diego, pp 777–782
Tavakoli R, Nabi M, Basten T, Goossens K (2015) Enhanced time-slotted channel hopping in wsns using non-intrusive channel-quality estimation. In: Proceedings of international conference on mobile ad hoc and sensor systems (MASS), Dallas
Thiele L, Chakraborty S, Naedele M (2000) Real-time calculus for scheduling hard real-time systems. In: The 2000 IEEE international symposium on circuits and systems, 2000. Proceedings. ISCAS 2000, Geneva, vol 4. IEEE, pp 101–104
Trujillo S, Crespo A, Alonso A, Perez J (2014) Multipartes: multi-core partitioning and virtualization for easing the certification of mixed-criticality systems. J Microprocess Microsyst 38(8, part B):921–932. Elsevier
Ungerer T, Bradatsch C, Gerdes M, Kluge F, Jahr R, Mische J, Fernandes J, Zaykov PG, Petrov Z, Boddeker B, Kehr S, Regler H, Hugl A, Rochange C, Ozaktas H, Casse H, Bonenfant A, Sainrat P, Broster I, Lay N, George D, Quinones E, Panic M, Abella J, Cazorla F, Uhrig S, Rohde M, Pyka A (2013) parmerasa – multi-core execution of parallelised hard real-time applications supporting analysability. In: Proceedings of Euromicro symposium on digital system design (DSD), Los Alamitos
Valencia J, van Horsen E, Goswami D, Heemels M, Goossens K (2016) Resource utilization and quality-of-control trade-off for a composable platform. In: Proceedings of design, automation and test in Europe conference and exhibition (DATE), Lausanne
Windsor J et al (2009) Time and space partitioning in spacecraft avionics. In: SMC-IT, Pasadena
Zhang H (1995) Service disciplines for guaranteed performance service in packet-switching networks. Proc IEEE 83(10):1374–1396
Acknowledgements
The development of CompSOC has been partially funded by European grants, including CATRENE CT217 RESIST; ARTEMIS 621429 EMC2, 621353 DEWI, 621439 ALMARVI, and ECSEL 692455 ENABLE-S3.
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Goossens, K. et al. (2017). NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_17
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DOI: https://doi.org/10.1007/978-94-017-7267-9_17
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