Abstract
Dynamic and partial reconfiguration of Xilinx FPGAs is a well known technique for runtime adaptive system design. The technique enables to substitute parts of a configuration while other regions stay operative without any disturbance. The advantage is the fact, that the spatial and temporal partitioning can be exploited with the goal to increase the performance and to reduce the power consumption due to the re-use of chip area. However, the feature of dynamic and partial reconfiguration can be further exploited. This novel kind of exploitation is described in this chapter. FPGAs still have to compete with other solutions like e.g., processor based designs if e.g., a restricted power budget is available for a specific application domain. In order to reduce the power consumption to a minimum, many devices use different kinds of power saving modes, called sleep-or hibernating modes. In these modes, the power supply of the device is reduced or even fully down. Taking this idea to the extreme, many devices in systems are only powered at run-time when it is necessary. If not, they are released from their power supply and do not drain current at all. Due to the fact that such a power down mode leads to a complete loss of data in SRAM based FPGAs, special techniques for such designs needs to be developed. The configuration has to be reloaded into the device every time when reattaching the power to the FPGA. This circumstance leads to restrictions for the device deployment in some electronic systems since in many cases the time a device may use to wake up is strictly limited. In several use cases, the configuration time of a SRAM based FPGA exceeds this limitation and forces designers to use processors instead of FPGAs. This chapter describes a way to decrease the configuration time of a design by exploiting the method of dynamic and partial reconfiguration in order to enable the usage of a sleep mode. With the presented method, the configuration time of any Xilinx SRAM based FPGA from the identical series (e.g., Spartan 3) is independent from the size of the used device.
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Meyer, J. et al. (2011). FPGA Startup Through Sequential Partial and Dynamic Reconfiguration. In: Voros, N., Mukherjee, A., Sklavos, N., Masselos, K., Huebner, M. (eds) VLSI 2010 Annual Symposium. Lecture Notes in Electrical Engineering, vol 105. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1488-5_17
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DOI: https://doi.org/10.1007/978-94-007-1488-5_17
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