Abstract
This paper describes the influence of leakage reduction techniques on 4:1 Multiplexer. The techniques investigated in this paper include multi-threshold (MTCMOS) and variable-threshold (VTCMOS). Impact of temperature sensitivity on power consumption is also evaluated. The CMOS transmission gate logic (TGL) is used to design a new 4:1 MUX, based on this design, it removes the degraded output, the NMOS and PMOS are combined together for strong output level with the gain in area is a central result of proposed MUX. The designed circuit is realized in 45 nm technology, with the power dissipation of 1.35 pW from a 0.7 V supply voltage. The MUX can operate well up to 200 Gb/s.
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Mishra, M., Akashe, S., Babu, S. (2013). Effect of MT and VT CMOS, on Transmission Gate Logic for Low Power 4:1 MUX in 45 nm Technology. In: Bansal, J., Singh, P., Deep, K., Pant, M., Nagar, A. (eds) Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012). Advances in Intelligent Systems and Computing, vol 202. Springer, India. https://doi.org/10.1007/978-81-322-1041-2_12
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DOI: https://doi.org/10.1007/978-81-322-1041-2_12
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