Abstract
With the rapid development of integrated circuit technology, soft error has increasingly become the major factor for the reliability of microprocessors. The researchers employ a variety of methods to reduce the influence of soft errors. Besides the lower delay and increasing bandwidth, 3D integration technology also has the ability of heterogeneous integration. STT-RAM is a new storage technology with broad prospects. The characteristic that STT-RAM is immune to soft errors makes it ideal candidate for improving reliability and STT-RAM can be integrated into the 3D chip through heterogeneous integration. In this paper, we proposed a selective replication mechanism for soft error rate reduction in hybrid reorder buffer architecture based on the 3D integration technology and STT-RAM. Instructions will be replicated or migrated to STT-RAM for reliability improvement in certain situations. The experimental results show that the soft error rate of the proposed hybrid structure is reduced by 15 % on average and the AVF decreased 54.3 % further on average through the in-buffer selective replication mechanism while the performance penalty is 2.8 %.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Shivakumar, P., Kistler, M., Keckler, S.W., et al.: Modeling the effect of technology trends on the soft error rate of combinational logic. In: Proceedings of the 2002 International Conference on Dependable Systems and Networks (DSN 2002), Bethesda, MD, USA, pp. 389–398. IEEE CS (2002)
Mitra, S., Seifert, N., Zhang, M., Shi, Q., Kim, K.S.: Robust system design with built-in soft-error resilience. IEEE Trans. Comput. 38(2), 43–52 (2005)
Baumann, R.C.: Radiation-Induced soft errors in advanced semiconductor technologies. IEEE Trans. Device Mater. Reliab. 5(3), 305–316 (2005)
Baumann, R.C: Soft errors in commercial semiconductor technology: overview and scaling trends. In: IEEE Reliability Physics Tutorial Notes, Reliability Fundamentals 7 April 2002
Zielger, J.F., Puchner, H.: SER—History, Trends and Challenges. Cypress Semiconductor Corporation, San Jose (2004)
Michalak, S.E., Harris, K.W., Hengartner, N.W., Takala, B.E., Wender, S.A.: Predicting the number of fatal soft errors in Los Alamos National Laboratory’s ASC Q supercomputer. Trans. Device Mater. Reliab. 5(3), 329–335 (2005)
Baumann, R.C.: Soft errors in advanced semiconductor Devices Part I: the three radiation sources. IEEE Trans. Device Mater. Reliab. 1, 17–22 (2001)
Banerjee, K., Souri, S.J., Kapur, P., Saraswat, K.C.: 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proc. IEEE 89(5), 602–633 (2001)
Xie, Y.: Processor architecture design using 3D integration technology. In: VLSID 2010, pp. 446–451 (2010)
Hosomi, M., Yamagishi, H.Y., Yamamoto, T., Bessho, K., Higo, Y., Yamane, K., Yamada, H., Shoji, M., Hachino, H., Fukumoto, C., Nagao, H., Kano, H.: A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM. In: IEDM 2005
Fu, X., Li, T., Fortes, J.: Sim-SODA: A unified framework for architectural level software reliability analysis. In: Proceedings of Workshop on Modeling, Benchmarking and Simulation (2006)
Sherwood, T., Perelman, E., Hamerly, G., Calder, B.: Automatically characterizing large scale program behavior. In: ASPLOS 2002
Mukherjee, S.S., Weaver, C.T., Emer, J., Reinhardt, S.K., Austin, T.: A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. In: MICRO 2003
Sun, H., Liu, C., Xu, W., Zhao, J., Zheng, N., Zhang, T.: Using magnetic RAM to build low-power and soft error-resilient L1 cache. IEEE Trans. VLSI 20(1), 19–28 (2010)
Sun, G., Kursun, E., Rivers, J., Xie, Y.: Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory. In: Proceedings of the 29th International Conference on Computer Design (ICCD) October 2011, pp. 366–372 (2011)
Zhang, W., Li, T.: Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology. In: Proceedings of the 41st Annual International Symposium on Micro-architecture (MICRO) December 2008, pp. 453–446 (2008)
Sun, H., Ren, P., Zheng, N., Zhang, T., Li, T.: Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology. Microprocess. Microsyst. 35(4), 371–381 (2011)
Tan, J., Li, Z., Fu, X.: Soft-error reliability and power co-optimization for GPGPUS register file using resistive memory. In: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE) March 2015, pp. 369–374 (2015)
Acknowledgments
The research is supported by National Natural Science Foundation of China with Grant No. 61076025, and by Specialized Research Fund for the Doctor Program of Higher Education of China with Grant No. 20124307110016.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Song, C., Zhang, M. (2016). Mitigating Soft Error Rate Through Selective Replication in Hybrid Architecture. In: Xu, W., Xiao, L., Li, J., Zhang, C. (eds) Computer Engineering and Technology. NCCET 2015. Communications in Computer and Information Science, vol 592. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-49283-3_5
Download citation
DOI: https://doi.org/10.1007/978-3-662-49283-3_5
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-662-49282-6
Online ISBN: 978-3-662-49283-3
eBook Packages: Computer ScienceComputer Science (R0)