Abstract
While FPGA and other reconfigurable technologies have dramatically increased in size and speed, memory technology has had only modest improvements. Relative to logic speeds, memory latency is virtually flat and physical constraints on external pins limit memory bandwidth. Unfortunately, the traditional cache hierarchy found in fixedfunction integrated circuits has evolved to support sequential processors and is ineffective for highly parallel architectures. This paper proposes a novel memory subsystem and computational model for reconfigurable architectures.
It envisions a system where computational cores are oversubscribed with atomic tasks and the memory subsystem enables (1) hiding of latency by enabling the cores to overlap computation and memory transactions and (2) the system to fully utilize the available memory bandwidth. The first step in this grand vision is to change the memory model. Instead of a byte-addressable, global address space, a named segment memory controller is introduced and an FPGA-based implementation presented in this paper.
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References
Albonesi, D.: Selective cache ways: on-demand cache resource allocation. In: Proceedings of the 32nd Annual International Symposium on Microarchitecture, MICRO-32, pp. 248–259 (1999)
Bertsimas, D., Nakazato, D.: The distributional little’s law and its applications. Operations Research 43(2), 298–310 (1995)
Frigo, M., Johnson, S.: Fftw: an adaptive software architecture for the fft. In: Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, vol. 3, pp. 1381–1384 (1998)
Huang, B., Sass, R., DeBardeleben, N., Blanchard, S.: Pydac: A resilient run-time framework for divide-and-conquer applications on a heterogeneous many-core architecture. In: The 6th Workshop on UnConventional High Performance Computing, UCHPC at Euro-Par 2013 (2013)
Johnson, J.R.: Automated performance tuning. In: Proceedings of the 4th International Workshop on Parallel and Symbolic Computation, PASCO 2010, pp. 20–21. ACM, New York (2010), http://doi.acm.org/10.1145/1837210.1837215
Kozyrakis, C., Patterson, D.: A new direction for computer architecture research. Computer 31(11), 24–32 (1998)
Njoroge, N., Casper, J., Wee, S., Teslyar, Y., Ge, D., Kozyrakis, C., Olukotun, K.: Atlas: a chip-multiprocessor with transactional memory support. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2007, pp. 3–8, EDA Consortium, San Jose (2007), http://dl.acm.org/citation.cfm?id=1266366.1266370
Kogge, P., et al.: Exascale computing study: Technology challenges in achieving exascale systems. Tech. Rep. TR-2008-13, DARPA Information Processing Techniques Office (IPTO) sponsored study (2008), http://www.cse.nd.edu/Reports/2008TR-2008-13.pdf
Rajasekhar, Y., Sass, R.: A first analysis of a dynamic memory allocation controller (dmac) core. In: Proceedings of the 2011 Symposium on Application Accelerators in High-Performance Computing, SAAHPC 2011, pp. 64–67. IEEE Computer Society, Washington, DC (2011), http://dx.doi.org/10.1109/SAAHPC.2011.23
Wulf, W.A., McKee, S.A.: Hitting the memory wall: implications of the obvious. SIGARCH Comput. Archit. News 23(1), 20–24 (1995), http://doi.acm.org/10.1145/216585.216588
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Rajasekhar, Y., Sass, R. (2014). A Novel Memory Subsystem and Computational Model for Parallel Reconfigurable Architectures. In: an Mey, D., et al. Euro-Par 2013: Parallel Processing Workshops. Euro-Par 2013. Lecture Notes in Computer Science, vol 8374. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-54420-0_44
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DOI: https://doi.org/10.1007/978-3-642-54420-0_44
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