Abstract
Coarse grained reconfigurable array (CGRA) is an architecture which offers hardware like high performance and software like flexibility. The two characteristics make CGRA an effective candidate for computational intensive applications. In this paper, we propose a novel cluster base CGRA architecture which achieves high efficiency of CGRA. The reconfigurable processing elements in CGRA clusters share complex function units and registers. Area is reduced due to the resource sharing and the performance is improved. Besides, an ant colony based mapping algorithm is proposed. Experiments show that the cluster base CGRA outperforms some existing architectures in the efficiency; the proposed mapping algorithm also outperforms other mapping heuristics.
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References
Compton, K., Hauck, S.: Reconfigurable computing: A survey of systems and software. ACM Computing Surveys 34(2), 171–210 (2002)
Mei, B., Vernalde, S., Verkest, D., Man, H.D., Lauwereins, R.: ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. In: Cheung, P.Y.K., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 61–67. Springer, Heidelberg (2003)
Shami, M.A., Hemani, A.: Partially reconfigurable interconnection network for dynamically reprogrammable resource array. In: IEEE 8th International Conference on ASIC, pp. 122–125. IEEE Press, New York (2009)
Liang, C., Huang, X.: Mapping Parallel FFT Algorithm onto Smart-Cell Coarse-Grained Reconfigurable Architecture. IEICE Transactions on Electronics E93-C(3), 407–415 (2010)
Ansaloni, G., Bonzini, P., Pozzi, L.: EGRA: A Coarse Grained Reconfigurable Architectural Template. IEEE Transactions on Very Large Scale Intergration (VLSI) Systems 19(6), 1062–1074 (2011)
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Zhou, L., Liu, H., Liu, D. (2013). A Novel CGRA Architecture and Mapping Algorithm for Application Acceleration. In: Xu, W., Xiao, L., Zhang, C., Li, J., Yu, L. (eds) Computer Engineering and Technology. NCCET 2013. Communications in Computer and Information Science, vol 396. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-41635-4_23
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DOI: https://doi.org/10.1007/978-3-642-41635-4_23
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-41634-7
Online ISBN: 978-3-642-41635-4
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