Abstract
A Tree-based 3D Multilevel FPGA architecture that unifies two unidirectional programmable interconnection network is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a multilevel network with the switch blocks placed at different tree levels using Butterfly-Fat-Tree network topology. Two dimensional layout development of a Tree-based multilevel interconnect is a major challenge for Tree-based FPGA. A 3D interconnect network technology leverage on Through Silicon Via (TSVs) to re-distribute the Tree interconnects, based on network delay and thermal considerations into multiple silicon layers is discussed. The impact of of Through Silicon Vias and performance improvement of 3D Tree-based FPGA are analyzed. We present an optimized physical design technology leverage on TSV, Thermal-TSV (TTSV), and thermal analysis. Compared to 3D Mesh-based FPGA, the 3D Tree-based FPGA design reduces the number of TSVs by 29% and leads to a performance improvement of 53% based on our place and route experiments.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Betz, V., Marquardt, A., Rose, J.: A New Packing Placement and Routing Tool for FPGA Research. In: Intl. Workshop on FPGA, pp. 213–222 (1997)
De Micheil, G., Pavlidis, V., Atienza, D., Leblebici, Y.: Design Methods and Tools for 3D integration. In: Symposium on VLSI Tech Digest of Technical Papers, pp. 182–183 (2011)
Beyne, E.: 3D Interconnection and Packaging: Impending reality or still a Dream? In: Proc. of IEEE Intl. Solid-state Circuits Conf (ISSCC 2004), CA, vol. 1, pp. 138–139 (February 2004)
Ababei, C., Feng, Y., Goplen, B.: “Placement and routing in 3D integrated circuits”. IEEE Design & Test of Computers 22(6), 520–531 (2005)
Betz, V., Rose, J., Marquardt, A.: Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, Dordrecht (1999)
Siozios, K., Bartzas, A., Soudris, D.: Architecture Level Exploration of Alternative schemes Targeting 3D FPGAs: A Software Supported Methodology. Intl. Journal of Reconfigurable Computing (2008)
Chiricescu, S., Leeser, M., Vai, M.M.: Design and analysis of a dynamically reconfigurable three-dimensional FPGA. IEEE Trans. Very Large Scale Integr (VLSI) Syst. 9(1), 186–196 (2001)
Lin, M., Gamal, A., Lu, Y., Wong, S.: Performance Benefits of Monolithically Stacked 3D-FPGA. In: Int. Symp. Field-Program. Gate Arrays, Monterey, CA (2006)
Lim, S.: TSV-Aware 3D Physical Design Tool Needs for Faster Mainstream Acceptance of 3D ICs. In: ACM DAC Knowledge Center (dac.com) (2010)
Marrakchi, Z., Mrabet, H., Amouri, E., Mehrez, H.: Efficient tree topology for FPGA interconnect network. In: ACM Great Lakes Symp. on VLSI 2008, pp. 321–326 (2008)
Marrakchi, Z., Mrabet, H., Farooq, U., Mehrez, H.: FPGA Interconnect Topologies Exploration. Int. J. Reconfig. Comp. (2009)
Gayasen, A., Narayanan, V., Kandemir, M., Rahman, A.: Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues. IEEE Trans. on VLSI Syst. 16(7), 882–893 (2008)
Pistorius, J., Hutton, M.: Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation. In: Proc. of the Intl. Workshop on System Level Interconnect Prediction, Monterey, Calif, USA, pp. 31–38 (April 2003)
Jang, D.M., Ryu, C., Lee, K.Y., et al.: Development and evaluation of 3-D SiP with vertically interconnected Through Silicon Vias (TSV). In: Proc. of the 57th Electronic Components and Technology Conf (ECTC 2007), USA, pp. 847–852 (May-June 2007)
Ayala, J., Sridhar, A., Pangracious, V., Atienza, D., Leblebici, Y.: Through Silicon Via-Based Grid for Thermal Control in 3D Chips. NanoNet (2009)
Emna, A., Hayder, M., Zied, M., Habib, M.: Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing ReConFig 2009, Mexico (2009)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Pangracious, V., Marrakchi, Z., Amouri, E., Mehrez, H. (2013). Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA. In: Brisk, P., de Figueiredo Coutinho, J.G., Diniz, P.C. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2013. Lecture Notes in Computer Science, vol 7806. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36812-7_19
Download citation
DOI: https://doi.org/10.1007/978-3-642-36812-7_19
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-36811-0
Online ISBN: 978-3-642-36812-7
eBook Packages: Computer ScienceComputer Science (R0)