Abstract
This paper presents a novel hardware architecture for fast principle component analysis (PCA). The architecture is developed based on generalized Hebbian algorithm (GHA). In the architecture, the updating of different synaptic weight vectors are divided into a number of stages. The results of precedent stages are used for the computation of subsequent stages for expediting training speed and lowering the area cost. The proposed architecture has been embedded in a system-on-programmable-chip (SOPC) platform for physical performance measurement. Experimental results show that the proposed architecture is an effective alternative for fast PCA in attaining both high performance and low computation time.
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Lin, SJ., Hung, YT., Hwang, WJ. (2010). Fast Principal Component Analysis Based on Hardware Architecture of Generalized Hebbian Algorithm. In: Cai, Z., Hu, C., Kang, Z., Liu, Y. (eds) Advances in Computation and Intelligence. ISICA 2010. Lecture Notes in Computer Science, vol 6382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-16493-4_51
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DOI: https://doi.org/10.1007/978-3-642-16493-4_51
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-16492-7
Online ISBN: 978-3-642-16493-4
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