Abstract
In this paper, a bandwidth reduction scheme and its VLSI implementation for H.264/AVC motion vector decoding component is proposed to save the DRAM traffic. In this component, the motion information including motion vector and reference index, for the co-located picture and the last decoded line, is stored in DRAM. In order to save the DRAM access, a partition based storage format is first applied to condense the MB level data. Then, a DPCM-based variable length coding method is utilized to reduce the data size of each partition. Finally, the total bandwidth is further reduced by combining the co-located and last-line information. Experimental results show that the bandwidth requirement for motion vector calculation can be reduced by 85%~98% on typical 1080p and QFHD sequences, with only 7.8k additional logic gates. This can contribute to near 20% bandwidth reduction for the whole video decoder system.
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Zhou, J., Zhou, D., He, G., Goto, S. (2010). A Bandwidth Reduction Scheme and Its VLSI Implementation for H.264/AVC Motion Vector Decoding. In: Qiu, G., Lam, K.M., Kiya, H., Xue, XY., Kuo, CC.J., Lew, M.S. (eds) Advances in Multimedia Information Processing - PCM 2010. PCM 2010. Lecture Notes in Computer Science, vol 6298. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-15696-0_6
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DOI: https://doi.org/10.1007/978-3-642-15696-0_6
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