Memory Sharing Approach for TMR Softcore Processor

SRAM-based field programmable gate arrays (FPGAs) are more susceptible to single event upsets compared to ASIC. We focus on triple modular redundancy (TMR) to ensure high reliability. Herein, we study the implementation of TMR on a softcore processor called “Base TMR” for considering design flexibility, and evaluate the resource usage and operating frequency. To resolve these problems, we propose two types of TMR designs: “Memory Shared TMR” and “Cache Enabled TMR.” Memory Shared TMR achieved efficient memory usage, but it reduced the operating frequency to about 25% in comparison with Base TMR. Cache Enabled TMR improved the operating frequency to a value similar to that of the base processor in exchange for 125% of memory usage overhead. Consequently, when implementing the TMR processor, we need to adopt an adequate TMR design by considering the trade-offs.

Authors and Affiliations

1. Graduate School of Science and Technology, Kumamoto University, 2-39-1 Kurokami, Kumamoto, 860-8555, Japan

   Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga & Toshinori Sueyoshi

Editors and Affiliations

1. Institut für Technik der Informationsverarbeitung (ITIV), Universität Karlsruhe (TH), 76128, Karlsruhe, Germany

   Jürgen Becker

2. ECIT Institute, Queen’s University Belfast, Queen’s Road, Queen’s Island, BT3 9DT, Belfast, UK

   Roger Woods

3. Bradley Department of Electrical and Electronic Engineering, Virginia Tech, 302 Whittemore (0111), 24061, Blacksburg, VA, USA

   Peter Athanas

4. Department of Electronic Engineering, National University of Ireland, Galway, Ireland

   Fearghal Morgan

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