Abstract
Individual Data Processing Units (DPUs) are commonly used for operational control and specific data processing of scientific space instruments. These instruments have to be suitable for the harsh space environment in terms of e.g. temperature and radiation. Thus they need to be robust and fault tolerant to achieve an adequate reliability. The Configurable System-on-Chip (SoC) solution based on FPGA has successfully demonstrated flexibility and reliability for scientific space applications like the Venus Express mission. Future space missions demand high-performance on board processing because of the discrepancy of extreme high data volume and low downlink channel capacity. Furthermore, in-flight reconfiguration ability and dynamic reconfigurable modules enhances the system with maintenance potential and at run-time adaptive functionality. To achieve these advanced design goals a flexible Network-on-Chip (NoC) is proposed for applications with high reliability, like space missions. The conditions for SRAM-based FPGA in space are outlined. Additionally, we present our newly developed NoC approach, System-on-Chip Wire (SoCWire) and outline its performance and suitability for robust dynamic reconfigurable systems.
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© 2009 Springer-Verlag Berlin Heidelberg
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Osterloh, B., Michalik, H., Fiethe, B. (2009). SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs. In: Berekovic, M., Müller-Schloer, C., Hochberger, C., Wong, S. (eds) Architecture of Computing Systems – ARCS 2009. ARCS 2009. Lecture Notes in Computer Science, vol 5455. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00454-4_8
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DOI: https://doi.org/10.1007/978-3-642-00454-4_8
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