Abstract
Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static CMOS gates: the power dissipated by input transitions that do not produce output switching. In this work, we present an experimental set-up that shows that this power component may contribute up to 59% of the total power consumption of a gate in modern technologies. This fact makes very important to include it into any accurate power model.
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Millan, A., Juan, J., Bellido, M.J., Guerrero, D., Ruiz-de-Clavijo, P., Viejo, J. (2009). Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_39
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DOI: https://doi.org/10.1007/978-3-540-95948-9_39
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