Abstract
In this paper, a design for a low-power 512-bit synchronous EEPROM with flash cells for passive UHF RFID tag chip is presented. Applied are low-power schemes such as dual power supply voltage(VDD=1.5V and VDDP=2.5V), clocked inverter sensing, voltage-up converter, IO interface, and Dickson charge pump using schottky diode. An EEPROM is fabricated with the 0.25μm- EEPROM process. Simulation results show that power dissipations are 8.34μW in the read cycle and 57.7μW in the write cycle, respectively. The layout size is 449.3μm × 480.67μm.
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Lee, JH. et al. (2007). A Low-Power 512-Bit EEPROM Design for UHF RFID Tag Chips. In: Shi, Y., van Albada, G.D., Dongarra, J., Sloot, P.M.A. (eds) Computational Science – ICCS 2007. ICCS 2007. Lecture Notes in Computer Science, vol 4490. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72590-9_106
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DOI: https://doi.org/10.1007/978-3-540-72590-9_106
Publisher Name: Springer, Berlin, Heidelberg
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