Abstract
The stack-based floating point unit (FPU) in the x86 architecture limits its floating point (FP) performance. The flat register file can improve FP performance but affect x86 compatibility. This paper presents an optimized two-phase floating point register renaming scheme used in implementing an x86-compliant processor. The two-phase renaming scheme eliminates the implicit dependencies between the consecutive FP instructions and redundant operations. As two applications of the method, the techniques used in the second phase of the scheme can eliminate redundant loads and reduce the mis-speculation ratio of the load-store queue. Moreover, the performance of a binary translation system that translates instructions in x86 to MIPS-like ISA can also be boosted by adding the related architectural supports in this optimized scheme to the architecture.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Hu, W., Zhang, F., Li, Z.: Microarchitecture of the Godson-2 processor. Journal of Computer Science and Technology 3, 243–249 (2005)
Patterson, D., Hennessy, J.: Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, San Francisco (1996)
Goddard, M.D., White, S.A.: Floating point stack and exchange instruction. US Patent Number: 5,857,089 Jan.5 (Jan. 5, 1999)
Clift, D.W., Arnold, J.M., Colwell, R.P., Glew, A.F.: Floating point register alias table fxch and retirement floating point register array. US Patent Number: 5,499,352 (Mar. 12, 1996)
Zhang, F.: Performance analysis and optimization of microprocessors. PHD Thesis, Institute of Computing Technology, Chinese Academy of Sciences (6) (2005)
Tang, F.: Research on dynamic binary translation and optimization. PHD Thesis, Institute of Computing Technology, Chinese Academy of Sciences (6) (2006)
Baraz, L., Devor, T., Etzion, O., Goldenberg, S., Skaletsky, A., Wang, Y., Zemach, Y.: IA-32 execution layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium®-based systems. MICRO-2003 (11) (2003)
Dehnert, J.C., Grant, B.K., Banning, J.P, Johnson, R., Kistler, T., Klaiber, A., Mattson, J.: The transmeta code morphing software: using speculation, recovery, and adaptive retranslation toaddress real-life challenges. CGO-2003 (3) (2003)
Bochs: The Open Source IA-32 Emulation Project. http://bochs.sourceforge.net/
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer Berlin Heidelberg
About this paper
Cite this paper
Qian, X. et al. (2007). Optimized Register Renaming Scheme for Stack-Based x86 Operations. In: Lukowicz, P., Thiele, L., Tröster, G. (eds) Architecture of Computing Systems - ARCS 2007. ARCS 2007. Lecture Notes in Computer Science, vol 4415. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71270-1_4
Download citation
DOI: https://doi.org/10.1007/978-3-540-71270-1_4
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-71267-1
Online ISBN: 978-3-540-71270-1
eBook Packages: Computer ScienceComputer Science (R0)