Abstract
During the design process of modern SoCs (systems on chip), system architects require the support of design tools and methods that allow for a precise exploration of promising solutions. A trend towards autonomic SoCs is being proposed, in which a system’s behavior is adapted at run time to improve reliability or power consumption. However, this opens ever more degrees of freedom in the definition of suitable architectures. Not only must the allocation and binding of resources and tasks be determined, but also the strategies by which an autonomic system adapts to changing working conditions. This paper presents an extension to the TAPES system simulator in order to support the evaluation of autonomic SoCs.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Lipsa, G., Herkersdorf, A.: Towards a Framework and a Design Methodology for Autonomic SoC. In: The 2nd IEEE International Conference on Autonomic Computing (June 2005)
Wild, T., Herkersdorf, A., Lee, G.-Y.: TAPES - Trace-based architecture performance evaluation with SystemC. Design Automation for Embedded Systems 10(2–3), 157–179 (2006)
Lankes, A., Wild, T., Zeppenfeld, J.: Power Estimation of Time Variant SoCs with TAPES. In: DSD 2007: 10th EUROMICRO Conference on Digital System Design: Architectures, Methods, Tools, EUROMICRO, pp. 261–264 (August 2007)
Kephart, J.O., Chess, D.M.: The Vision of Autonomic Computing. Computer 36(1), 41–50 (2003)
Brinkschulte, U., Becker, J., Dorfmüller-Ulhaas, K., et al.: CARUSO - Project Goals and Principal Approach. In: Workshop on Organic Computing, GI Jahrestagung, Ulm (September 2004)
De Micheli., G.: Robust System Design with Uncertain Information. In: MEMOCODE 2003: Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), p. 283. IEEE Computer Society Press, Washington (2003)
Gries, M.: Methods for evaluating and covering the design space during early design development. Integr. VLSI J. 38(2), 131–183 (2004)
Thiele, L., Wandeler, E.: Performance Analysis of Distributed Embedded Systems. Embedded Systems Handbook (2005)
Henia, R., et al.: System level performance analysis - the SymTA/S approach. IEEE Proceedings Computers and Digital Techniques 152(2), 148–166 (2005)
Cai, L., Gajski, D.: Transaction level modeling: an overview. In: CODES+ISSS 2003: Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 19–24. ACM Press, New York (2003)
SystemC Homepage, www.systemc.org
Donlin, A.: Transaction level modeling: flows and use models. In: CODES+ISSS 2004: Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 75–80. ACM Press, New York (2004)
Paulin, P.G., Pilkington, C., Bensoudane, E.: StepNP: A System-Level Exploration Platform for Network Processors. IEEE Design and Test of Computers 19(6), 17–26 (2002)
Ramaswamy, R., Wolf, T.: PacketBench: A tool for workload characterization of network processing. In: IEEE 6th Annual Workshop on Workload Characterization (WWC-6), Austin (October 2003)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2008 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Lankes, A., Wild, T., Zeppenfeld, J. (2008). System Level Simulation of Autonomic SoCs with TAPES. In: Brinkschulte, U., Ungerer, T., Hochberger, C., Spallek, R.G. (eds) Architecture of Computing Systems – ARCS 2008. ARCS 2008. Lecture Notes in Computer Science, vol 4934. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-78153-0_3
Download citation
DOI: https://doi.org/10.1007/978-3-540-78153-0_3
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-78152-3
Online ISBN: 978-3-540-78153-0
eBook Packages: Computer ScienceComputer Science (R0)