Abstract
To reduce power consumption in electronic designs, new techniques for circuit design must always be considered. Float ing-gate MOS (FGMOS) is one of those techniques and has previously shown poten tially better performance than standard static CMOS circuits for ultra-low power designs. One reason for this is because FGMOS only requires a few transis tors per gate and still retain a large fan-in. Another reason is that CMOS circuits becomes very slow in subthreshold region and are not suitable in many applications while FGMOS can have a shift in threshold voltage to increase speed performance. This paper investigates how the performance of an FGMOS full-adder circuit will compare with two common CMOS full-adder designs. Simulations in a 120 nm process shows that FGMOS can have up to 9 times better EDP performance at 250 mV. The simulations also show that the FGMOS full-adder is 32 times faster and have two orders of magnitude higher power consumption than that for CMOS.
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Alfredsson, J., Aunet, S. (2007). Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_52
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DOI: https://doi.org/10.1007/978-3-540-74442-9_52
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