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Abstract

Power has become the most important candidate for optimization in today’s design. This is necessary for further functionality and processing capability to be added to the design. Standard cell design is the defacto standard for most IC designs. The other end of the spectrum is full custom design whose efficiency is very high, but with a large design time. In this paper we investigate the use of prototype module generators to improve the energy efficiency of the design over the standard cell design while trading off some design time. We investigate this on an interconnect intensive design namely the SIMD Shuffler which is one of the important parts of a low power embedded processor’s datapath. We show that using module generators, we can reduce the energy consumption of the shuffler by about 30%. We also show the possible research opportunities for filling in the further EDA tools for low power.

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References

  1. Van Berkel, K., Heinle, F., Meuwissen, P., Moerman, K., Weiss, M.: Vector processing as an enabler for software-defined radio in handsets from 3G+WLAN onwards. In: Proc. of Software Defined Radio Technical Conference, November 2004, pp. 125–130 (2004)

    Google Scholar 

  2. Rounioja, K., Puusaari, K.: Implementation of an hsdpa receiver with a customized vector processor. In: Proc of SOC (November 2006)

    Google Scholar 

  3. Lin, Y., Lee, H., Woh, M., Harel, Y., Mahlke, S., Mudge, T., Chakrabarti, C., Flautner, K.: SODA: A low-power architecture for software radio. In: Proc of ISCA (2006)

    Google Scholar 

  4. DeMan, H.: Ambient intelligence: Giga-scale dreams and nano-scale realities. In: Proc of ISSCC, Keynote Speech (February 2005)

    Google Scholar 

  5. Chinnery, D., Keutzer, K.: Closing the Gap Between ASIC and Custom: Tools and Techniques for High-Performance ASIC Design. Springer, Heidelberg (2006)

    Google Scholar 

  6. Chinnery, D., Keutzer, K.: Closing the Power Gap Between ASIC and Custom: Tools and Techniques for Low Power Design. Springer, Heidelberg (2006)

    Google Scholar 

  7. Wiess, O., Gansen, M., Noll, T.G.: A flexible datapath generator for physical oriented design. In: Proc of ESSCIRC, September 2001, pp. 408–411 (2001)

    Google Scholar 

  8. IBM: The Cell Microprocessor (2005), http://www.research.ibm.com/cell/

  9. Texas Instruments, Inc, http://focus.ti.com/docs/apps/catalog/resources/appnote abstract.jhtml?abstractName=spru732b. TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide, May 2006.

    Google Scholar 

  10. Philips PDSL. CF6 CoolFlux DSP (2004), http://www.coolfluxdsp.com

  11. Cadence and TSMC, Cadence-TSMC Reference Flow ver. 6.0 (2005), http://www.cadence.com/datasheets/6159_TSMC_RefFlow_FS_FNL.pdf

  12. Chinnery, D., Keutzer, K.: Closing the power gap between asic and custom: an asic perspective. In: Proc of DAC, pp. 275–280 (2005)

    Google Scholar 

  13. Six, P., Claesen, L., Rabaey, J., De Man, H.: An intelligent module generator environment. In: Proc of DAC, pp. 730–735 (1986)

    Google Scholar 

  14. Raghavan, P., Munaga, S., Rey Ramos, E., Lambrechts, A., Jayapala, M., Catthoor, F., Verkest, D.: On the benefits of customized cross-bar for data-shuffling operation in simd asip. In: ARCS 2007. LNCS, vol. 4415, Springer, Heidelberg (2007)

    Chapter  Google Scholar 

  15. Padmanabhan, K.: Design and analysis of even-sized binary shuffle-exchange networks for multiprocessors. IEEE Transactions on Parallel and Distributed Systems 385–397 (1991)

    Google Scholar 

  16. McGregor, J.P., Lee, R.B.: Architecture techniques for acclerating subword permutations with repetitions. Trans. on VLSI, 325–335 (2003)

    Google Scholar 

  17. Diana Smith, S., Siegel, H.J.: An emulator network for SIMD machine interconnect networks. Computers, 232–241 (1979)

    Google Scholar 

  18. RWTH Aachen – University of Technology, DPG User Manual Version 2.8 (October 2005), http://www.eecs.rwth-aachen.de/dpg/info.html

  19. Gemmeke, T., Gansen, M., Noll, T.G.: Implementation of scalable power and area efficient high-throughput viterbi decoders. IEEE Journal of Solid-State Circuits 37(7) (July 2002)

    Google Scholar 

  20. Gemmeke, T., Gansen, M., Noll, T.G.: Design optimization of low power high performance dsp building blocks. IEEE Journal of Solid-State Circuits 39(7), 1131–1139 (2004)

    Article  Google Scholar 

  21. Cadence Inc.: Cadence Virtuoso Custom Design Platform (2006), http://www.cadence.com/products/custom_ic/index.aspx

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Nadine Azémard Lars Svensson

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© 2007 Springer-Verlag Berlin Heidelberg

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Raghavan, P. et al. (2007). Semi Custom Design: A Case Study on SIMD Shufflers. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_42

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  • DOI: https://doi.org/10.1007/978-3-540-74442-9_42

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-74441-2

  • Online ISBN: 978-3-540-74442-9

  • eBook Packages: Computer ScienceComputer Science (R0)

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