Abstract
In this paper we present a model for delay and slew calculation in on chip bus structures respectively parallel routed wires. Capacitive coupling is often neglected during circuit design although it can have significant influence on the wire delay. The model takes capacitive coupling effects into account. It is based on interpreting the impulse response of a linear circuit as a probability distribution function. Closed-form equations are derived for length dependent moment calculations in integrated bus structures as well as for the effects on the wire delay and output slew. The model is suitable for performance evaluation and optimization.
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© 2004 Springer-Verlag Berlin Heidelberg
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Tahedl, M., Pfleiderer, HJ. (2004). Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_9
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DOI: https://doi.org/10.1007/978-3-540-30205-6_9
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
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