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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3254))

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Abstract

In this paper, we propose the White-box Table-based Total Power Consumption (WTTPC) estimation approach that offers both rapid and accurate architecture-level power estimation models for some processor components with regular structures, such as SRAM arrays, based on WTTPC-tables of power values. A comparison of power estimates obtained from the proposed approach against circuit-level HSPICE power values for a 64-b conventional 6T-SRAM memory array implemented in a commercial 0.13-um CMOS technology process shows a 98% accuracy of the WTTPC approach.

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References

  1. Ferre, A., Figueras, J.: Characterization of Leakage Power in CMOS Technologies. In: Proc. of the IEEE Intl. Conf. on Electronics, Circuits and Systems, Lisbon, Portugal, September 1998, vol. 2, pp. 185–188 (1998)

    Google Scholar 

  2. SIA, International Roadmap for Semiconductors (2001)

    Google Scholar 

  3. Brooks, D., et al.: Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In: Proc. of ISCA, Vancouver, BC, Canada, June 2000, pp. 83–94 (2000)

    Google Scholar 

  4. Butts, J.A., Sohi, G.S.: A Static Power Model for Architects. In: Proc. of the Intl. Symp. on Micro-architectures, Monterey, CA, USA, December 2000, pp. 191–201 (2000)

    Google Scholar 

  5. Parikh, D., et al.: Comparison of State-Preserving vs. Non-State-Preserving Leakage Control in Caches. In: Proc. of the Workshop on Duplicating, Deconstructing and Debunking (held in conjunction with ISCA), San Diego, CA, USA, June 2003, pp. 14–25 (2003)

    Google Scholar 

  6. Mamidipaka, M., et al.: Leakage Power Estimation in SRAMs, Technical Report No. 03- 32, Center for Embedded Computer Systems, University of California, Irvine, USA (September 2003)

    Google Scholar 

  7. Schmidt, E., et al.: Memory Power Models for Multilevel Power Estimation and Optimization. IEEE Transaction on VLSI Systems 10, 106–109 (2002)

    Article  Google Scholar 

  8. Eckerbert, D., Larsson-Edefors, P.: A Deep Submicron Power Estimation Methodology Adaptable to Variations Between Power Characterization and Estimation. In: Proc. of the 2003 Asia-South Pacific Design Automation Conf., Kitakyushu, Japan, January 2003, pp. 716–719 (2003)

    Google Scholar 

  9. Do, Q.M., Bengtsson, L., Larsson-Edefors, P.: DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architecture. In: Proc. of Parallel and Distributed Computing and Networks Symp (PDCN), Innsbruck, Austria, February 2003, pp. 767–772 (2003)

    Google Scholar 

  10. Do, Q.M., Bengtsson, L.: Analytical Models for Power Consumption Estimation in the DSP-PP Simulator: Problems and Solutions, Technical Report No. 03-22, Chalmers University of Technology, Göteborg, Sweden (August 2003)

    Google Scholar 

  11. Eckerbert, D.: Power Estimation and Multi-Phase Clock Generation for the Deep Submicron Era, Ph.D dissertation, Chalmers University of Technology, Göteborg, Sweden (2003)

    Google Scholar 

  12. Gupta, S., Najm, F.N.: Power modeling for high level power estimation. IEEE Transactions on VLSI Systems 8, 18–29 (2000)

    Article  Google Scholar 

  13. Gowan, M.K., et al.: Power Considerations in the Design of the Alpha 21264 Microprocessor. In: Proc. of Design Automation Conf., San Francisco, CA, USA, June 1998, pp. 726–731 (1998)

    Google Scholar 

  14. Montanaro, J., et al.: A 160-Mhz, 32-b, 0.5-W CMOS RISC Microprocessor. IEEE Journal of Solid-state Circuits 31, 1703–1714 (1996)

    Article  Google Scholar 

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© 2004 Springer-Verlag Berlin Heidelberg

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Do, M.Q., Larsson-Edefors, P., Bengtsson, L. (2004). Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_89

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  • DOI: https://doi.org/10.1007/978-3-540-30205-6_89

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-23095-3

  • Online ISBN: 978-3-540-30205-6

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