Abstract
This work analyses the effects on timing and power consumption of the inductive coupling in long high-frequency on-chip interconnects. By means of extensive simulations it is shown that the common assumptions used until now when considering only line inductance effects do not hold. In fact, signal integrity, voltage glitches and cross-talk, signal delay, rise and fall times, as well as power dissipation strongly depend on the mutual inductances and the input data toggling pattern.
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References
Chandrakasan, A.P., Brodersen, R.W.: Low Power Digital CMOS Design. Kluwer Academic Publishers, Dordrecht (1995)
Cheng, C.-K., Lillis, J., Lin, S., Chang, N.: Interconnect Analysis and Synthesis. John Wiley & Sons, Chichester (2000)
El-Moursy, M.A., Friedman, E.G.: Inductive Interconnect Width Optimization for Low Power. In: Intl. Symposium on Circuits and Systems (ISCAS) (May 2003)
Gala, K., Blaauw, D., Wang, J., Zolotov, V., Zhao, M.: Inductance 101: Analysis and Design Issues. In: Design Automation Conference (DAC) (June 2001)
He, L., Chang, N., Lin, S., Nakagawa, O.S.: An Efficient Inductance Modeling for On-Chip Interconnects. In: IEEE Custom Integrated Circuits Conference, pp. 457–460 (1999)
Ismail, Y., Friedmann, E.G., Neves, J.L.: Figures of Merit to Characterize the Importance of On-Chip Inductance. IEEE Trans. on VLSI Systems 7, 442–449 (1999)
Kamon, M., Tsuk, M., White, J.: FastHenry: A Multipole-Accelerated 3D Inductance Extraction Program. IEEE Trans. on Microwave Theory and Techniques (1994)
Lin, S., Chang, N., Nakagawa, S.: Quick On-Chip Self- and Mutual-Inductance Screen. In: Intl. Symposium on Quality Electronic Design, March 2000, pp. 513–520 (2000)
Massoud, Y., Ismail, Y.: Grasping the Impact of On-Chip Inductance. IEEE Circuits & Devices Magazine, 14–21 (July 2001)
Nabors, K., White, J.: FastCap: A Multipole-Accelerated 3D Capacitance Extraction Program. IEEE Trans. on CAD of Integrated Circuits and Systems (1991)
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Murgan, T., Ortiz, A.G., Schlachta, C., Zimmer, H., Petrov, M., Glesner, M. (2004). On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_84
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DOI: https://doi.org/10.1007/978-3-540-30205-6_84
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
Online ISBN: 978-3-540-30205-6
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