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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3254))

Abstract

Numerous Dynamic Voltage Scaling (DVS) methods have been proposed over the years, and since several commercial programmable processors supporting DVS are now available, the demand for DVS evaluation tools is obvious. In this paper we propose a simulator based on soft- and hardware parameters that make it possible to get realistic performance evaluations from a high abstraction level. Traditionally, DVS methods have been tested using unrealistic assumptions, both from a software and hardware point of view, but this problem is now alleviated due to our simulator. We show that DVS methods are very depended on the application specification as well as the processor parameters.

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References

  1. Shin, D., Kim, W., Jeon, J., Kim, J.: SimDVS: An Integrated Simulation Environment for Performance Evaluation of Dynamic Voltage Scaling Algorithms. In: Falsafi, B., VijayKumar, T.N. (eds.) PACS 2002. LNCS, vol. 2325, pp. 98–113. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  2. Kim, W., Shin, D., Yun, H.S., Kim, J., Min, S.L.: Performance Comparison of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems. In: Proceedings of the Eighth IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), September 2002, pp. 219–228 (2002)

    Google Scholar 

  3. Shin, D., Kim, J., Lee, S.: Intra-Task Voltage Scheduling for Low-Energy Hard Real-Time Applications. IEEE Design and Test of Computers 18(23), 20–30 (2001)

    Google Scholar 

  4. Gruian, F.: Hard Real-Time Scheduling Using Stochastic Data and DVS Processors. In: Proceedings of International Symposium on Low Power Electronics and Design, pp. 46–51 (2001)

    Google Scholar 

  5. Shin, Y., Choi, K., Sakurai, T.: Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. In: Proceedings of International Conference on Computer-Aided Design, pp. 365–368 (2000)

    Google Scholar 

  6. Pillai, P., Shin, K.G.: Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems. In: Operating Systems Review (ACM), 18th ACM Symposium on Operating Systems Principles (SOSP 2001), pp. 89–102 (2002)

    Google Scholar 

  7. Aydin, H., Melhem, R., Mosse, D., Alvarez, P.M.: Dynamic and Aggressive Scheduling Techniques for Power-Aware Real-Time Systems. In: Proceedings of Real-Time Systems Symposium, pp. 95–105 (2001)

    Google Scholar 

  8. Kim, W., Kim, J., Min, S.L.: A Dynamic Voltage Scaling Algorithm for Dynamic- Priority Hard Real-Time Systems Using Slack Time Analysis. In: Proceedings of the Design Automation and Test in Europe (DATE), March 2002, pp. 788–794 (2002)

    Google Scholar 

  9. Mudge, T.: Power: A First Class Design Constraint for Future Architectures. IEEE Computer 32(4), 52–58 (2001)

    Google Scholar 

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© 2004 Springer-Verlag Berlin Heidelberg

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Olsen, A.B., Büttner, F., Koch, P. (2004). On Combined DVS and Processor Evaluation. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_34

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  • DOI: https://doi.org/10.1007/978-3-540-30205-6_34

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-23095-3

  • Online ISBN: 978-3-540-30205-6

  • eBook Packages: Springer Book Archive

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