Abstract
Clustered L0 buffers are an interesting alternative for reducing energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 clusters is performed as an hardware optimization, where the compiler generates a schedule and based on the given schedule L0 clusters are synthesized. The result of clustering is schedule dependent, which offers a design space for exploring the effects on clustering by scheduling. This paper presents a study indicating the potentials offered by shuffling operations within a VLIW instruction on L0 cluster synthesis. The simulation results indicate that potentially up to 75% of L0 buffer energy can be reduced by shuffling operations.
This work is supported in part by MESA under the MEDEA+ program.
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Jayapala, M., Aa, T.V., Barat, F., Catthoor, F., Corporaal, H., Deconinck, G. (2004). L0 Cluster Synthesis and Operation Shuffling. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_33
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DOI: https://doi.org/10.1007/978-3-540-30205-6_33
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