Abstract
This paper presents an approach for simulation of mixed analog-digital CMOS integrated circuits, aiming at estimating crosstalk effects due to current pulses drawn from voltage supplies. A simple expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate is derived, and a representation of digital switching noise in time domain can be easily calculated through a dedicated computer program. This representation is used to perform an analog simulation using SPICE, to evaluate the propagation of the switching noise through the parasitic elements of the package and of the bonding wires. Simulation results for two case studies are presented.
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Trucco, G., Boselli, G., Liberali, V. (2004). A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2004. Lecture Notes in Computer Science, vol 3254. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30205-6_16
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DOI: https://doi.org/10.1007/978-3-540-30205-6_16
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23095-3
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