Abstract
We present a Field Programmable Logic Devices (FPLDs) based implementation of a scalable filter architecture capable of detecting and removing impulsive noise in image sequences. The adaptive filter architecture is built using switching spatiotemporal filtering scheme and robust Lower-Upper-Middle (LUM) based noise detector. It uses highly optimized bit-serial pipelined implementation in Altera FPLDs. The proposed architecture provides real-time performance for 3-D image processing with sampling frequencies up to 97 Mpixels/second.
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Drutarovský, M., Fischer, V. (2004). Implementation of a 3-D Switching Median Filtering Scheme with an Adaptive LUM-Based Noise Detector. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_151
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DOI: https://doi.org/10.1007/978-3-540-30117-2_151
Publisher Name: Springer, Berlin, Heidelberg
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