Abstract
Design of the hardware implementation of the CAESAR competition second round candidate, HS1-SIV, with regular cipher parameter settings is described in this paper. Given implementation of HS1-SIV cipher was developed in such a way to be conforming to the specification of the authenticated cipher as well as a hardware API. The implemented API is conforming to the specifications of the GMU Hardware API for authenticated ciphers. The VHDL implementation was synthesized using Xilinx XST High Level Synthesis for the target device Xilinx Virtex-7. We achieved a throughput over 120 Mbit/s utilizing area of 103,214 LUTs for the cipher implementation with the data length of the message and the associated data set at 64 bytes and the length of the key set at 32 bytes. Based on the performance results obtained hardware API overhead was calculated which is equal to 8% for 8-byte data length and 15% for 2048-byte data length when compared to the cipher-core.
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Acknowledgements
We would like to thank Ted Krovetz for answering our questions regarding HS1-SIV. Also, our thanks go out to Antonio de la Piedra and Kostas Papagiannopoulos for their support and technical expertise.
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Volokitin, S., Geltink, G. (2017). Hardware Implementation of HS1-SIV. In: Obaidat, M. (eds) E-Business and Telecommunications. ICETE 2016. Communications in Computer and Information Science, vol 764. Springer, Cham. https://doi.org/10.1007/978-3-319-67876-4_9
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DOI: https://doi.org/10.1007/978-3-319-67876-4_9
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