Abstract
A mathematical model for the output signal’s energy of a multidimensional ideal DAC is presented considering sampling clock jitter. More specifically, a new model is formulated to prove one-sided energy inequality for the output signal, for which the base time is affected by the jitter. Moreover, a family of annihilate operators is defined and applied to the ideal (one-dimensional) DAC model to estimate the output signal energy.
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Loreti, P., Ahrabi, S.S., Vellucci, P. (2018). Mathematical Model for the Output Signal’s Energy of an Ideal DAC in the Presence of Clock Jitter . In: Madani, K., Peaucelle, D., Gusikhin, O. (eds) Informatics in Control, Automation and Robotics . Lecture Notes in Electrical Engineering, vol 430. Springer, Cham. https://doi.org/10.1007/978-3-319-55011-4_20
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