Abstract
Using Artificial Intelligence (AI) techniques has become the best solution in many applications. By the end of Moore's Law, implementing a platform capable of such massive processing for edge-IoT applications has become a significant challenge. However, using static hardware accelerators can be an excellent solution; even so, they typically require a great deal of silicon area and are not optimized for all operation modes. Reconfigurable computing lets parts of the hardware change proportionally to the task during operation, allowing for optimized operation and the use of many hardware accelerators without requiring a large area. In this study, we present a dynamic acceleration unit exchange on a RISC-V soft-processor based on the open-source Klessydra-T13 RISC-V core. We show how reconfiguration can be used to make the hardware accelerator more flexible and improve its performance. As a case study, we show how reconfiguration techniques can be used to speed up AI architectures by reconfiguration of vector accelerator units.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Wang, X., et al.: Convergence of edge computing and deep learning: a comprehensive survey (2020)
Sordillo, S., et al.: Customizable vector acceleration in extreme-edge computing: a RISC-V software/hardware architecture study on VGG-16 implementation. Electronics 10(4), 518 (2021)
Cao, J., Zhang, Q., Shi, W.: Edge Computing: A Primer. Springer (2018)
Koch, D.: Partial Reconfiguration on FPGAs; Architectures, Tools and Applications. Springer (2013). https://doi.org/10.1007/978-3-030-02083-5
Zuchowski, P.S., et al.: A hybrid ASIC and FPGA architecture. In: IEEE/ACM International Conference on Computer Aided Design (2002)
Cheikh, A., et al.: Klessydra-T: Designing vector coprocessors for multithreaded edge-computing cores. IEEE Micro 41(2) (2021)
Cheikh, A., et al.: Efficient mathematical accelerator design coupled with an interleaved multi-threading RISC-V microprocessor. In: ApplePies 2019 (2019). https://doi.org/10.1007/978-3-030-37277-4_62
Cheikh, A., et al.: The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes. LNEE, vol. 512, pp. 89–97 (2019). https://doi.org/10.1007/978-3-319-93082-4_12
Olivieri, M., et al.: Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores. In: Proceedings 1st New Generation of CAS, NGCAS 2017, pp. 45–48 (2017)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2023 The Author(s), under exclusive license to Springer Nature Switzerland AG
About this paper
Cite this paper
Jamili, S. et al. (2023). Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor. In: Berta, R., De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2022. Lecture Notes in Electrical Engineering, vol 1036. Springer, Cham. https://doi.org/10.1007/978-3-031-30333-3_40
Download citation
DOI: https://doi.org/10.1007/978-3-031-30333-3_40
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-031-30332-6
Online ISBN: 978-3-031-30333-3
eBook Packages: EngineeringEngineering (R0)