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An Automated Logic-Level Framework for Approximate Modular Arithmetic Circuits

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Approximate Computing

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Abstract

The manual design techniques for approximate arithmetic circuits are very time-demanding as they require optimal trade-offs among the hardware savings and the approximation error. Therefore, there is a need to automate this design process so that multiple approximate design points can be generated from the original circuit. In this chapter, we present an automated framework called approximate solution finder (ASF) that exploits logic-level approximations under a given error constraint to design approximate arithmetic circuits. Our proposed methodology improves on existing state-of-the-art manual design techniques and is evaluated by using them in error-tolerant case studies such as image sharpening and canny edge detection.

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Authors and Affiliations

  1. Nanjing University of Aeronautics and Astronautics, Nanjing, China

    Haroon Waris, Chenghua Wang & Weiqiang Liu

Authors
  1. Haroon Waris
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  2. Chenghua Wang
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  3. Weiqiang Liu
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Corresponding author

Correspondence to Haroon Waris .

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Editors and Affiliations

  1. Nanjing University of Aeronautics and Astronautics, Nanjing, China

    Weiqiang Liu

  2. Northeastern University, Boston, MA, USA

    Fabrizio Lombardi

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Waris, H., Wang, C., Liu, W. (2022). An Automated Logic-Level Framework for Approximate Modular Arithmetic Circuits. In: Liu, W., Lombardi, F. (eds) Approximate Computing. Springer, Cham. https://doi.org/10.1007/978-3-030-98347-5_2

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  • DOI: https://doi.org/10.1007/978-3-030-98347-5_2

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-98346-8

  • Online ISBN: 978-3-030-98347-5

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