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FastCache: A Client-Side Cache with Variable-Position Merging Schema in Network Storage System

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Algorithms and Architectures for Parallel Processing (ICA3PP 2021)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 13156))

Abstract

Cache plays an important role in providing high throughput and low latency network storage service for I/O intensive applications. One major challenge is that performance of storage degrades significantly even with cache at backend while facing microwrite workload. A straightforward approach is to use cache at client to merge microwrites into sequential write. However, we notice that direct merging within block causes severe fragments problem. Specifically, simple cache update policy pollutes cache which leads to I/O performance degradation. In this paper, we introduce FastCache, a two level of cache based on hash table and linked list to store data slice and variable-position merging schema to convert random microwrites into sequential write. To avoid cache pollution, we design a new cache update policy based on measurable threshold to control flushing and Poisson distribution sampling to find the most suitable entries to be evicted. We implement FastCache in FastCFS and conduct extensive evaluations under benchmark FIO and real workload. We show that FastCache outperforms LRU and HCCache in terms of IOPS and access latency. The experimental results demonstrate that IOPS can be improved by up to 10\(\times \), and the access latency with FastCache decreases by 50%–90%.

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Acknowledgement

This research was supported by Jiangsu Provincial Key Research and Development Program under Grant BE2020001-3, the National Natural Science Foundation of China under Grant 61832005 and 6217220, China Southern Power Grid Shenzhen Digital Power Grid Research Institute CGY21001.

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Correspondence to BaoLiu Ye .

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Qian, L., Ye, B., Wang, X., Qu, Z., Duan, W., Zhao, M. (2022). FastCache: A Client-Side Cache with Variable-Position Merging Schema in Network Storage System. In: Lai, Y., Wang, T., Jiang, M., Xu, G., Liang, W., Castiglione, A. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2021. Lecture Notes in Computer Science(), vol 13156. Springer, Cham. https://doi.org/10.1007/978-3-030-95388-1_10

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  • DOI: https://doi.org/10.1007/978-3-030-95388-1_10

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  • Print ISBN: 978-3-030-95387-4

  • Online ISBN: 978-3-030-95388-1

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