Abstract
Designing high-end full-custom VLSI systems such as microprocessors is a very complex engineering task, involving hundreds of man-years’ effort. Hierarchical design methodology is essential for handling the complexity of the task. Fueled by Moore’s Law, market competition and economic considerations dictate the introduction of new products in the so-called “Tick-Tock” strategy. The Tick-Tock development strategy delivers a new product manufactured in the most advanced stable technology (named “old technology”). It is then followed by delivering chips of the same architecture, but in a new, scaled manufacturing process technology (named “new technology”), thus allowing higher production volumes, better performance, and lower cost. An essential part of the second phase is the conversion of the underlying physical layout, comprising billions of polygons, into the new technology. Such conversion is known in VLSI jargon as hard-IP reuse [Nitzan 02]. An enabler for this strategy is therefore the automation of layout conversion from older into newer technology. Such automation is a very challenging computational task that must satisfy complex geometric rules, hence translated into an optimization problem involving billions of variables and constraints.
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Moiseev, K., Kolodny, A., Wimer, S. (2015). Layout Migration. In: Multi-Net Optimization of VLSI Interconnect. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0821-5_9
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DOI: https://doi.org/10.1007/978-1-4614-0821-5_9
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