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Multi-net Sizing and Spacing in General Layouts

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Multi-Net Optimization of VLSI Interconnect

Abstract

In the previous chapters, the sizing of bundles of parallel wires has been discussed. However, bundle structures are usually formed at the higher metal layers and, even in these layers, they are only a part of the whole layout. In this chapter, general or random layout structures, their modeling and optimization, will be discussed.

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Moiseev, K., Kolodny, A., Wimer, S. (2015). Multi-net Sizing and Spacing in General Layouts. In: Multi-Net Optimization of VLSI Interconnect. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0821-5_7

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  • DOI: https://doi.org/10.1007/978-1-4614-0821-5_7

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  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-0820-8

  • Online ISBN: 978-1-4614-0821-5

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