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Data scheduling to increase performance of parallel accelerators

  • Custom Computing and Codesign
  • Conference paper
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Field-Programmable Logic and Applications (FPL 1997)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1304))

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Abstract

The paper presents a general data and task scheduling technique for parallel accelerators with one or more processing modules and the capability for local and shared memory access. Multiple tasks and their data are mapped onto the processing modules and the host, providing a high degree of parallelism. The system performance is enhanced by avoiding unnecessary data transfers. It is shown, how overall system performance can be increased by appropriate data distribution.

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References

  1. A. Ast, J. Becker, R. Hartenstein, R. Kress, H. Reinig, K. Schmidt: Data-procedural Languages for FPL-based Machines; 4th Int. Workshop on Field Programmable Logic and Appl., FPL'94, Prague, Sept. 7-10,1994, Springer, 1994

    Google Scholar 

  2. A. Ast, R. Hartenstein, H. Reinig, K. Schmidt, M. Weber: A General Purpose Xputer Architecture derived from DSP and Image Processing. In Bayoumi, M.A. (Ed.): VLSI Design Methodologies for Digital Signal Processing Architectures, Kluwer Academic Publishers 1994.

    Google Scholar 

  3. J. Becker, R. W. Hartenstein, R. Kress, H. Reinig: High-Performance Computing Using a Reconfigurable Accelerator; Proc. of Workshop on High Performance Computing, Montreal, Canada, July 1995

    Google Scholar 

  4. J.Becker: A Partitioning Compiler for Computers with Xputer-based Accelerators, Ph.D. dissertation, Kaiserslautern University, 1997

    Google Scholar 

  5. Reiner W. Hartenstein, Helmut Reinig: Novel Sequencer Hardware for High-Speed Signal Processing; Workshop on Design Methodologies for Microelectronics, Smolenice Castle, Slovakia, September 1995

    Google Scholar 

  6. R. Hartenstein, et al.: A Datapath Synthesis System for the Reconfigurable Datapath Architecture; ASP-DAC'95, Makuhari, Chiba, Japan, Aug. 29–Sept. 1, 1995

    Google Scholar 

  7. Reiner W. Hartenstein, Jurgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger: A Parallelizing Programming Environment for Embedded Xputerbased Accelerators; High Performance Computing Symposium `96, Ottawa, Canada, June 1996

    Google Scholar 

  8. R. Hartenstein, J. Becker, M. Herz, U. Nageldinger: A General Approach in System Design Integrating Reconfigurable Accelerators; Proc. of IEEE 1996 Int'l. Conference on Innovative Systems in Silicon; Austin, Texas, USA, Oct. 9–11, 1996

    Google Scholar 

  9. R. W. Hartenstein, J. Becker, R. Kress, H. Reinig, K. Schmidt: A Reconfigurable Machine for Applications in Image and Video Compression; Conf. on Compression Techniques & Standards for Image & Video Compression, Amsterdam, Netherlands, March 1995

    Google Scholar 

  10. Reiner W. Hartenstein, Jurgen Becker, Rainer Kress: Custom Computing Machines vs. Hardware/Software Co-Design: from a globalized point of view; 6th International Workshop On Field Programmable Logic And Applications, FPL'96, Darmstadt, Germany, September 23-25, 1996, Lecture Notes in Computer Science, Springer Press, 1996

    Google Scholar 

  11. R. Hartenstein, A. Hirschbiel, K. Schmidt, M. Weber: A novel Paradigm of Parallel Computation and its Use to implement Simple High-Performance Hardware; Future Generation Computing Systems 7 (1991/92), p. 181–198

    Article  Google Scholar 

  12. A. Hirschbiel: A Novel Processor Architecture Based on Auto Data Sequencing and Low Level Parallelism; Ph.D. Thesis, University of Kaiserslautern, 1991

    Google Scholar 

  13. R. Kress: A fast reconfigurable ALU for Xputers; Ph. D. dissertation, Kaiserslautern University, 1996

    Google Scholar 

  14. K. Schmidt: A Program Partitioning, Restructuring, and Mapping Method for Xputers; Ph.D. Thesis, University of Kaiserslautern, 1994

    Google Scholar 

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Wayne Luk Peter Y. K. Cheung Manfred Glesner

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© 1997 Springer-Verlag Berlin Heidelberg

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Hartenstein, R.W., Becker, J., Herz, M., Nageldinger, U. (1997). Data scheduling to increase performance of parallel accelerators. In: Luk, W., Cheung, P.Y.K., Glesner, M. (eds) Field-Programmable Logic and Applications. FPL 1997. Lecture Notes in Computer Science, vol 1304. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63465-7_234

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  • DOI: https://doi.org/10.1007/3-540-63465-7_234

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-63465-2

  • Online ISBN: 978-3-540-69557-8

  • eBook Packages: Springer Book Archive

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