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The instruction systolic array — Implementation of a low-cost parallel architecture as add-on board for personal computers

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High-Performance Computing and Networking (HPCN-Europe 1994)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 797))

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Abstract

In this paper the architecture of a 1024 processor instruction systolic array is described. Besides the presentation of the concept and the architectural details of this novel type of massively parallel system the paper focusses on the problems that had to be solved during the development phase.

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References

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Wolfgang Gentzsch Uwe Harms

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© 1994 Springer-Verlag Berlin Heidelberg

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Schimmler, M., Lang, HW., Maaß, R. (1994). The instruction systolic array — Implementation of a low-cost parallel architecture as add-on board for personal computers. In: Gentzsch, W., Harms, U. (eds) High-Performance Computing and Networking. HPCN-Europe 1994. Lecture Notes in Computer Science, vol 797. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57981-8_165

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  • DOI: https://doi.org/10.1007/3-540-57981-8_165

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-57981-6

  • Online ISBN: 978-3-540-48408-0

  • eBook Packages: Springer Book Archive

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