Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations

1. R. A. Fisher. Statistical Methods, Experimental Design, and Scientific Inference. Oxford University Press, 1993. Reprinted, with corrections, from earlier versions, 1925–1973.

   Google Scholar 

2. R. E. Bryant. Graph-based algorithms for Boolean function manipulation. IEEE Trans. Computers, C-35(8):677–691, August 1986.

   Google Scholar 

3. R. Rudell. Dynamic variable ordering for ordered binary decision diagrams. In Proceedings of the International Conference on Computer Aided Design, pages 42–47, November 1993.

   Google Scholar 

4. M. R. Mercer, R. Kapur, and D. E. Ross. Functional approaches to generating orderings for efficient symbolic representations. In Proceedings of the 29th ACM/IEEE Design Automation Conference, pages 624–627, June 1992.

   Google Scholar 

5. S. Panda, F. Somenzi, and B. F. Plessier. Symmetry detection and dynamic variable ordering of decision diagrams. In Proceedings of the International Conference on Computer Aided Design, pages 628–631, November 1994.

   Google Scholar 

6. E. M. Sentovich. A brief study of BDD package performance. In Proceedings of FMCAD 96, number 1166 in LNCS, pages 389–403, 1996.

   Google Scholar 

7. F. Brglez and H. Fujiwara. Special Session on ATPG(Also introducing’ A Neutral Netlist of 10 Combinational Benchmark Circuits’). In Int. Symp. On Circuits and Systems, 1985. Now a benchmark directory ISCAS85 at http://www.cbl.ncsu.edu/benchmarks/Benchmarks-upto-1996.html.

8. F. Brglez, D. Bryan, and K. Kozminski. Combinational profiles of sequential benchmark circuits. In IEEE 1989 International Symposium on Circuits and Systems-ISCAS89, pages 1924–1934, May 1989. A basis for a benchmark directory IS-CAS89, now archived at http://www.cbl.ncsu.edu/benchmarks/.

9. S. Yang. Logic Synthesis and Optimization Benchmarks User Guide. Technical Report 1991-IWLS-UG-Saeyang, MCNC, Research Triangle Park, NC, January 1991. Now available from: http://www.cbl.ncsu.edu/publications/#1991-IWLS-UG-Saeyang And benchmarks from: http://www.cbl.ncsu.edu/benchmarks/Benchmarks-upto-1996.html.

10. D. Ghosh, N. Kapur, J. E. Harlow, and F. Brglez. Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. In Proceedings, Design Automation and Test in Europe, pages 656–663, Feb 1998. Also available at http://www.cbl.ncsu.edu/publications/#1998-DATE-Ghosh.

11. N. Kapur, D. Ghosh, and F. Brglez. Towards A New Benchmarking Paradigm in EDA: Analysis of Equivalence Class Mutant Circuit Distributions. In ACM International Symposium on Physical Design, April 1997. Also available from http://www.cbl.ncsu.edu/publications/#1997-ISPD-Kapur.

12. F. Brglez. Design of Experiments to Evaluate CAD Algorithms: Which Improvements Are Due to Improved Heuristic and Which Are Merely Due to Chance? Technical Report 1998-TR@CBL-04-Brglez, CBL, CS Dept., NCSU, Box 7550, Raleigh, NC 27695, April 1998. Also available at http://www.cbl.ncsu.edu/publications/#1998-TR@CBL-04-Brglez.

13. J. E. Harlow and F. Brglez. Design of Experiments in BDD Variable Ordering: Lessons Learned. In Proceedings of the International Conference on Computer Aided Design. ACM, November 1998. Also available from http://www.cbl.ncsu.edu/publications/#1998-ICCAD-Harlow.

14. The VIS Group. VIS: A system for verification and synthesis. In R. Alur and T. Henzinger, editors, Proceedings of the 8th International Conference on Computer Aided Verification, number 1102 in Lecture Notes in Computer Science, pages 428–432, New Brunswick, NJ, July 1996. Springer. Version 1.2 is available from UC Berkeley Design Technology Warehouse at http://www-cad.eecs.berkeley.edu/Software/software.html.

    Google Scholar 

15. F. Somenzi et al. Colorado University Decision Diagram package (CUDD), release 2.1.2, 1997. Available from ftp://vlsi.colorado.edu/pub/cudd-2.1.2.tar.gz.

16. D. E. Long. CMU BDD package, 1993. Available from: http://emc.cmu.edu/pub/bdd/bddlib.tar.Z.

17. J. Calhoun and F. Brglez. A Framework and Method for Hierarchical Test Generation. IEEE Transactions on Computer-Aided Design, 11(1):45–67, January 1992.

    Google Scholar 

18. K. A. Brownlee. Statistical Theory and Methodology In Science and Engineering. Krieger Publishing, 1984. Reprinted, with revisons, from second edition, 1965.

    Google Scholar 

19. J. C. Hsu. Multiple Comparisons: Theory and Methods. Chapman & Hall, 1996.

    Google Scholar 

20. K. Iwama and K. Hino. Randomgeneration of test instances for logic optimizers. In Proceedings of the 31st ACMIEEE Design Automation Conference, pages 430–434, 1994.

    Google Scholar 

21. A. Žemva and F. Brglez. Detectable Perturbations: A Paradigm for Technology Specific Multi-Fault Test Generation. In VLSI Test Symposium, pages 350–357, April 1995. Also available from: http://www.cbl.ncsu.edu/publications/#1995-VTS-Zemva-p350.

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