Abstract
A development environment for FPGAs has been created, which allows to build a data-flow system easily by assembling pre-designed components. To get a high-level, platform independent description we introduce Active Components. They contain several implementations for several hardware platforms and ensure correct usage of the communication interface. This offers an improved portability and reusability compared to standard FPGA modules. A comparison with a hand-crafted implementation shows its applicability without any serious drawback in resource utilization and performance.
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Rühl, S., Dillinger, P., Hezel, S., Männer, R. (2001). Generative Development System for FPGA essors with Active Components . In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_53
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DOI: https://doi.org/10.1007/3-540-44687-7_53
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