Abstract
This paper proposes a new parallel algorithm and architecture for two modular multiplications over GF(2m). The algorithm uses the property of irreducible all one polynomial as a modulus and computes two modular multiplications in parallel. The architecture is based on cellular automata and has smaller area and time complexity than previous architectures. Since the proposed architecture has regularity, modularity and concurrency, it is suitable for VLSI implementation. The proposed architecture can be used as a basic architecture for the public-key cryptosystems.
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References
I. S. Reed and T. K. Truong, “The use of finite fields to compute convolutions,” IEEE Trans. on Information Theory, IT-21, pp. 208–13, Mar. 1975.
B. Schneier, Applied Cryptography-second edition, John Wiley&Sons, Inc. 1996.
V. Neumann, The theory of self-reproducing automata, Univ. of Illinois Press, Urbana & London, 1966.
S. Wolfram, “Statistical mechanics of cellular automata,” Rev. of Modern Physics, vol. 55, pp. 601–644, 1983.
W. Pries, A. Thanailakis, and H. C. Card, “Group properties of cellular automata and VLSI applications,” IEEE Trans. on Computers, C-35, vol. 12, pp. 1013–1024, Dec. 1986.
E. R. Berlekamp, Algebraic Coding Theory, New York: McGraw-Hill, 1986.
C. S. Yeh. S. Reed, and T. K. Truong, “Systolic multipliers for finite fields GF(2m),” IEEE Trans. on Computers, vol. C-33, pp. 357–360, Apr. 1984.
S. K. Jain and L. Song, “Efficient Semisystolic Architectures for finite field Arithmetic,” IEEE Trans. on VLSI Systems, vol. 6, no. 1, pp. 101–113, Mar. 1998.
J. L. Massey and J. K. Omura, Computational method and apparatus for finite field arithmetic, U. S. Patent application, submitted 1981.
S. W. Wei, “A systolic power-sum circuit for GF(2m),” IEEE Trans. on Computers, vol. 43, pp. 226–229, Feb. 1994.
T. Itoh and S. Tsujii, “Structure of parallel multipliers for a class of finite fields GF(2m),” Info. Comp., vol. 83, pp. 21–40, 1989.
S. T. J. Fenn, M. G. Parker, M. Benaissa, and D. Taylor, “Bit-serial Multiplication in GF(2m) using irreducible all one polynomials,” IEE. Proc. Comput. Digit. Tech., vol. 144, no. 6, Nov. 1997.
H. S. Kim, Bit-Serial AOP Arithmetic Architecture for Modular Exponentiation, Ph. D. Thesis, Kyungpook National Univ., 2002.
P. Pal. Choudhury and R. Barua, “Cellular Automata Based VLSI Architecture for Computing Multiplication and Inverses in GF(2m),” IEEE 7 th International Conference on VLSI Design, Jan. 1994.
D. E. Knuth, The Art of Computer Programming. Volume 2: Seminumerical Algorithms, Addison-Wesley, Reading, Massachusetts, 2nd edition, 1998.
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Kim, HS., Yoo, KY. (2002). Parallel Algorithm and Architecture for Public-Key Cryptosystem. In: Shafazand, H., Tjoa, A.M. (eds) EurAsia-ICT 2002: Information and Communication Technology. EurAsia-ICT 2002. Lecture Notes in Computer Science, vol 2510. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36087-5_17
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DOI: https://doi.org/10.1007/3-540-36087-5_17
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