Nothing Special   »   [go: up one dir, main page]

Skip to main content

Minimizing Cost and Minimizing Schedule Length in Synthesis of Fault Tolerant Multiprocessors Systems

  • Conference paper
Parallel Processing and Applied Mathematics (PPAM 2005)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3911))

  • 847 Accesses

Abstract

The paper includes a proposal of a new approach of synthesis of fault tolerant multiprocessors systems. Optimal task scheduling and optimal partition at resources are basic problems in high-level synthesis of computer systems. Coherent synthesis may have a practical application in developing tools for computers aided design of such systems.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. Berrojo, L., Corno, F., Entrena, L., Gonzales, I., Lopez, C., Sonza Reorda, M., Squillero, G.: An industrial environment for high-level fault tolerant structures insertion and validation. In: Proc. 20th IEEE VLSI Test Symp. Monterey, pp. 229–236 (2002)

    Google Scholar 

  2. Blazewicz, J., Drabowski, M., Weglarz, J.: Scheduling multiprocessor tasks to minimize schedule length. IEEE Trans. Computers C-35(5), 389–393 (1986)

    Article  MathSciNet  MATH  Google Scholar 

  3. Chen, L., Dey, S., Sanchez, P., Sekar, K., Chen, Y.: Embedded hardware and software self-testing methodologies for processor cores. In: Proc. 37th Design Automation Conf., Los Angeles, pp. 625–630 (2000)

    Google Scholar 

  4. Drabowski, M.: Co-synthesis of real time system. In: Processing of IX Conference Real time systems. The Silesian University of Technology, pp. 279–289 (2002)

    Google Scholar 

  5. Drabowski, M.: Coherent synthesis of real time systems – the neural approach. In: Modern problems of Real Time Systems, WNT, Warszawa, pp. 13–24 (2004)

    Google Scholar 

  6. Drabowski, M., Czajkowski, K.: Coherent Synthesis of Heterogeneous System - a Tabu Search Approach. In: Proceedings of Artificial Intelligence Studies. Proceedings on VII Int. Conference AI’20/2005, Siedlce, vol. 2(25), pp. 139–147 (2005)

    Google Scholar 

  7. Drabowski, M., Czajkowski, K.: Task scheduling in coherent co-synthesis of computer system. In: Image Analysis, Computer Graphics, Security Systems and Artificial Intelligence Applications, Bialystok, vol. 15, pp. 53–62 (2005)

    Google Scholar 

  8. Drabowski, M., Wantuch, E.: Coherent concurrent tasks scheduling and resources assignment in dependable system design. In: Proc. of European Safety & Reliability Conference, London, pp. 487–495 (2005)

    Google Scholar 

  9. Drabowski, M., Wantuch, E.: Concurrent synthesis of heterogeneous information systems - deterministic approach. In: Proceedings of Int. Congress InBus, Krakow, pp. 53–58 (2004)

    Google Scholar 

  10. Oh., H., Ha, S.: Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints. In: Proceedings of tenth Int. Conf. on Hardware / Software codesign, pp. 133–138. IEEE Computer Society Press, Los Alamitos (2002)

    Google Scholar 

  11. Xie, Y., Li, L., Kandemir, M., Vijaykrishnan, N., Irwin, M.J.: Reliability-aware Cosynthesis for Embedded Systems. In: Proc. of ASAP 2004, pp. 41–50 (2004)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2006 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Drabowski, M., Czajkowski, K. (2006). Minimizing Cost and Minimizing Schedule Length in Synthesis of Fault Tolerant Multiprocessors Systems. In: Wyrzykowski, R., Dongarra, J., Meyer, N., Waśniewski, J. (eds) Parallel Processing and Applied Mathematics. PPAM 2005. Lecture Notes in Computer Science, vol 3911. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11752578_119

Download citation

  • DOI: https://doi.org/10.1007/11752578_119

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-34141-3

  • Online ISBN: 978-3-540-34142-0

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics