Abstract
EISC (Extendable Instruction Set Computer) is a compressed code architecture developed for embedded applications and has higher code density than its competing architectures. In this paper, we propose a low-power DSP-enhanced embedded microprocessor based on the 32-bit EISC architecture. We present how we could exploit the special features, and how we could overcome the deficits, of the EISC architecture to accelerate DSP applications while adding relatively low hardware overhead. Our simulation results show that the proposed DSP-enhanced processor reduces the execution time of the considered DSP kernels by 77.6% and the MP3 applications by 30.9%. The proposed DSP enhancements cost approximately 10300 gates (18%) and do not increase the clock frequency. While the high code density of EISC would be of great advantage to a low-power embedded system, the proposed DSP enhancement could increase its power consumption by 16.9%. We show that a set of supports for power management could reduce the power consumption by 65.5%. The proposed processor has been embedded in an SoC for video processing and proven in silicon.
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References
Francis, H.: ARM DSP-Enhanced Instructions White Paper, http://arm.com/pdfs/ARM-DSP.pdf
MIPS Tech. Inc.: Architecture Set Extension, http://www.mips.com/content/Documentation/MIPSDocumentation/ProcessorArchitecture/doclibrary
Cho, K.Y.: A Study on Extendable Instruction Set Computer 32 bit Microprocessor. J. Inst. of Electronics Engineers of Korea 36-D(55), 11–20 (1999)
Lee, H., Beckett, P., Appelbe, B.: High-Performance Extendable Instruction Set Computing. In: Proc. of 6th ACSAC 2001, pp. 89–94 (2001)
Kim, H.-G., Jung, D.-Y., Jung, H.-S., Choi, Y.-M., Han, J.-S., Min, B.-G., Oh, H.-C.: AE32000B: A Fully Synthesizable 32-bit Embedded Microprocessor Core. ETRI Journal 25(5), 337–344 (2003)
Lee, C., Potkonjak, M.: MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. In: MICRO-30, pp. 330–335 (1997)
ARM Ltd.: The Thumb Architecture Extension, http://www.arm.com/products/CPUs/archi-thumb.html
Kissell, K.D.: MIPS16: High-density MIPS for the Embedded Market, MIPS Tech. Inc., http://www.mips.com/Documentation/MIPS16whitepaper.pdf
Bunda, J.D.: Instruction-Processing Optimization Techniques for VLSI Microprocessors, PhD thesis, The University of Texas at Austin (1993)
Park, G.-C., Ahn, S.-S., Kim, H.-G., Oh, H.-C.: Supports for Processing Media Data in Embedded Processors. Poster Presentation, HiPC2004 (2004)
Cho, K.Y., Lim, J.Y., Lee, G.T., Oh, H.-C., Kim, H.-G., Min, B.G., Lee, H.: Extended Instruction Word Folding Apparatus, U.S. Patent No.6,631,459 (2003)
Kim, H.-G.: AE32000: Hardware User Guide, http://adc.co.kr/Korean/Products/ProdDocu/ae32000b_hw_ug_v1.1_031118e.pdf
Talla, D., John, L.K., Buger, D.: Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements. IEEE Tras. of Comp. 52(8), 1015–1021 (2003)
Hennessy, J.L., Patterson, D.A.: Computer Architecture; A Quantitative Approach, 3rd edn. Morgan Kaufmann Publishers, San Francisco (2003)
Jayaraj, J., Rajendran, P.L., Thirumoolam, T.: Shadow Register File Architecture: A Mechanism to Reduce Context Switch Latency. In: HPCA-8 (2002) Poster Presentation
Samsung Electronics: STD130 0.18um 1.8V CMOS Standard Cell Library for Pure Logic Products Data Book, Samsung Electronics (2001)
Advanced Digital Chips Inc.: GMX1000: A High Performance Multimedia Processor User Manual, Advanced Digital Chips Inc. (2005)
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Kim, HG., Oh, HC. (2005). A Low-Power DSP-Enhanced 32-Bit EISC Processor. In: Conte, T., Navarro, N., Hwu, Wm.W., Valero, M., Ungerer, T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2005. Lecture Notes in Computer Science, vol 3793. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11587514_20
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DOI: https://doi.org/10.1007/11587514_20
Publisher Name: Springer, Berlin, Heidelberg
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