5.5 Conclusions
The notion of designing a packet switching fabric on a chip was introduced and studied from a pragmatic as well as technological perspective. It has been argued that in the context of emulating an output-queued switch, a core challenge pertains to the memory-management algorithm employed. A proposed packet-placement algorithm and related architecture were described in detail, emphasizing the feasibility attributes. The switch model and framework presented can be broadened to further investigate the notion of consolidating multiple switch fabric functions on silicon.
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Elhanany, I., Tabatabaee, V., Matthews, B. (2007). Fabric on a Chip: A Memory-management Perspective. In: Elhanany, I., Hamdi, M. (eds) High-performance Packet Switching Architectures. Springer, London . https://doi.org/10.1007/1-84628-274-8_5
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DOI: https://doi.org/10.1007/1-84628-274-8_5
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